And what will / may happen if the two master SCL frequencies are very different = so much that even when starting at the same SCL falling edge they will be opposite in phase before 9 SCL pulses are through.
(I am aware of how I2C works, have read the specs and know about the general role of master and slave and about arbitration)
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2 Answers
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Given that a master device defines the clock rate at which slaves receive and respond, it's unlikely that there will be any problem. Only one master has control of the bus so, comparison between one master's clock rate and another's is of no consequence to the practical working of connected devices. Arbitration is performed when two masters try to access near-simultaneously and, differences in clock speed won't come into play.
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The bus is synchronous so they can differ by any amount.
Within reason, of course.
Multiple masters trying to transmit simultaneously must be able to arbitrate, so the slowest device driving the bus defines the clock. So the clocks cannot go into different phase like you suggest.
Whatever clocks each master uses when transmitting on the bus, the only limitation is that all other chips (masters or slaves) have to be able to follow it, whether or not more than one device tries to communicate at the same time.
Obviously a master capable of up to 400 kHz Fast Mode cannot function on a bus where another master communicates at 1 MHz Fast Mode Plus mode.
But if both masters are capable of following/monitoring the bus up to 400 kHz Fast Mode, then one can use 1 Hz when generating the clock and other can use 400 kHz.
The actual limitation is your implementation, not a generic limitation that comes from the standard.
Basically, any amount your MCUs or other I2C implementation allows.
