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I am using SGM2052 LDO in my design. Using its fixed voltage version.In the datasheet you can see that it has a pin called Vbias.

The description of Vbias is given below.

enter image description here

Below is the typical application circuit.

enter image description here

What I understood from the datasheet is we need to connect a separate voltage at BIAS pin.

My question is can I connect Vbias to Vin as shown below?.

enter image description here

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2 Answers 2

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It's a NMOS LDO:

enter image description here

Let's look at the curves. Dropout voltage (between VIN and VOUT) can be very low as the left graph shows. But the NMOS gate needs to be biased to a voltage above VOUT, which is provided via BIAS pin. So you need sufficient voltage between BIAS and OUT: up to 1.2V, as the right graph shows.

enter image description here

The curves are only typical, and the table states BIAS should be 1.6V above OUT, to ensure it works in all cases.

So if you connect VIN and VBIAS, this LDO becomes a HDO (High dropout regulator) and the dropout voltage is indicated by the plot on the right. If you want to get 1.2V from 3.3V, then it's absolutely fine. If you want to get 2.5V from 3.3V, then nope.

To get 3.3V from 5V, that's 1.7V difference so it will work. If the 5V is actually 5V +/-5% then the lower bound of that (4.75V) is too low.

Thermal resistance is quite high (it's a tiny chip) so when operating at high dropout, power dissipation needs to be taken into account.

Also note that PSRR and dropout voltage have a special relationship. When the regulator is in dropout (when it operates at its minimum input voltage to still maintain the output voltage), the MOSFET acts like a resistor: it has no PSRR at all. This is why, while they brag about "low dropout" and "ultra high PSRR" you do not get both at the same time. And if you look at the fine print, the PSRR curves are measured at 0.5V dropout, far from the minimum. It's still quite good. But if you operate it at above 1.6V dropout as recommended, you will get the datasheet PSRR or better.

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  • \$\begingroup\$ I need 3.3V from 5V \$\endgroup\$
    – Confused
    Mar 28 at 12:10
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    \$\begingroup\$ It's more than 1.6V drop so it's fine. If the input is 4.5-5.5V then nope. Watch out for dissipated power though. It's a tiny chip. \$\endgroup\$
    – bobflux
    Mar 28 at 12:11
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What I understood from the datasheet is we need to connect a separate voltage at BIAS pin.

Yes.

Block diagrams on p.9 clearly show that the BIAS pin is the supply voltage of the internal error amplifier and maybe some other blocks as well.

My question is can I connect Vbias to Vin as shown below?.

The ELECTRICAL CHARACTERISTICS section gives you an acceptable voltage range for VBIAS pin:

enter image description here

So the BIAS pin voltage should be at least 2.5V or higher than the nominal output voltage by at least 1.6V. Whichever is greater.

$$ \mathrm{V_{BIAS}=max(2.5 \text{ VDC}, V_{OUT} \text{ + 1.6 VDC})} $$

For example, if the output (adjusted is fixed) is 0.6 VDC then you should apply at least 2.5 VDC to the BIAS pin. If the input is 3.3V then yes, you can connect the BIAS to VIN directly. But if the input is 1.8V then no, you can't.

Likewise, if the output is 3.3 VDC then you should apply at least 4.9 VDC to BIAS pin. If the input is 5 VDC then yes, you can connect VBIAS to VIN directly. But if the input is 3.6 VDC then no, you can't.

The maximum you can apply is 5.5 VDC.

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  • \$\begingroup\$ My input is 5V and output is 3.3V \$\endgroup\$
    – Confused
    Mar 28 at 12:07
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    \$\begingroup\$ @Hari see the updated answer, especially the last 2 paragraphs. \$\endgroup\$ Mar 28 at 12:10

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