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I am using the PCIe block of Altera Cyclone IV FPGA, and I have an issue whereby about half the PCIe slots I have tried (on three different computers) do not work.

Debugging with SignalTap shows that the LTSSM (Link Training and Status State Machine) gets stuck on state 3, which is the "polling compliance" state where "all voltage, noise emission and timing specifications are within tolerance".

Altera has a support page but it is not relevant to the Cyclone IV. Some chaps using TI hardware also had a similar problem.

Strangely, given a computer, some of the ports always work, and some of the ports always fail, which suggests (fingers crossed) that my design is not out of spec. I have checked that each PCIe port I have tried is at least gen2 and has at least 4 lanes.

What could cause the LTSSM to be stuck on "polling compliance"? How can I further debug the problem?

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I've recently completed a PCIe design using Altera's PCIe block. I was using the soft core on a Cyclone IV E part. I ended up in the same state and a number of things contributed:

  • not enough filtering on the PHY power supplies
  • a timing error caused by one of the SSTL-2-II signal traces being significantly longer than the others
  • The PCIe trace pair lengths being far too long

In the end the filtering was easy to fix, as was adjusting the SDC file so that P&R could adjust the I/O delays. The nasty part was correcting the excessively long (and out of spec, I think it worked out to something like 11 inches!) PCIe trace pairs. Once this was done through a re-route the core came up immediately and performed flawlessly.

The PHY we were using also seemed to be transmitting "quietly" -- the vendor claimed they were transmitting as per spec but analysis and measurement with some very expensive rental equipment could not verify their claim. If they were transmitting to spec we should have been able to get away with the long PCIe traces.

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  • \$\begingroup\$ Thanks. Two questions. 1) Did your design work on certain slots, but not others? 2) How did you fix the filtering on the PHY power supplies? \$\endgroup\$ – Randomblue May 29 '13 at 9:27
  • \$\begingroup\$ It didn't work reliably in any slot until the issues were resolved, but it certainly didn't favour one slot over another. The PHY filtering was just a lot of reading the datasheet, cutting supplies apart that we had put together and filtering them with capacitance, isolating with inductors. \$\endgroup\$ – akohlsmith May 29 '13 at 20:50
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The LTSSM will transition from Polling.Active to Polling.Compliance when electrical idle exit is not detected on any lanes where a receiver was detected. The LTSSM will then stay in Polling.Compliance until electrical idle is exited on any of those lanes.

Are all the lanes connected to valid receivers?

The other common way to enter Polling.Compliance is to have the LTSSM be directed into that state by higher level logic. This will most likely be some configuration bit in the Altera logic that lets you force the LTSSM into entering Polling.Compliance.

For further details check out the book "PCI-Express System Architecture."

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