I am using the PCIe block of Altera Cyclone IV FPGA, and I have an issue whereby about half the PCIe slots I have tried (on three different computers) do not work.
Debugging with SignalTap shows that the LTSSM (Link Training and Status State Machine) gets stuck on state 3, which is the "polling compliance" state where "all voltage, noise emission and timing specifications are within tolerance".
Strangely, given a computer, some of the ports always work, and some of the ports always fail, which suggests (fingers crossed) that my design is not out of spec. I have checked that each PCIe port I have tried is at least gen2 and has at least 4 lanes.
What could cause the LTSSM to be stuck on "polling compliance"? How can I further debug the problem?