# Comparator Using Common Gate CMOS

I am currently in the process of designing and testing a CMOS Comparator based of a Common Gate Topology.

Below is an extract of the ref circuit I am using:

The authors in the paper mention "Transistors M0 and M1 are each biased with a current Iref, while arranged as a source-coupled voltage comparator. One branch of Iref flows through the resistor Rref to generate a reference voltage Vref, while a second matched current flows into capacitor C and slowly charges the voltage VC. Initially, VC is reset to ground, causing Vcmp to be pulled low. Once VC exceeds Vref, M1 amplifies the voltage difference (VC−Vref) and Vcmp rises, triggering a digital clock buffer to generate a pulse Vrst which in turn resets VC. Unlike most voltage-mode relaxation oscillators, no additional comparator stage is required, thanks to the re-use of Iref for both charging the capacitor and biasing the comparator."

I'm not sure why the CG- AMP would amplify the difference between Vc and Vref, rather than just Vref, since in small signal the gate becomes shorted (unless this is large signal gain)?

It would be nice to get an intuitive understanding of what the Author means. Thanks.

This is a large-signal effect, and in general, you'll often need large-signal effects to discuss comparators (which often turn stages fully on/off, slew them significantly, etc).

Assume that M0 and M1 are matched. The current-mirror structure around M0 sets the shared gate net to $$\V_\text{ref}R_\text{ref} + V_\text{gs}\$$, where $$\V_\text{gs}\$$ is the large-signal bias point where M0 and M1 would have a current of $$\I_\text{ref}\$$ flow.

When $$\V_c\$$ > $$\V_\text{ref}\$$ (in the large-signal sense), $$\V_\text{gs,M1} < V_\text{gs}\$$ and M1 cuts off, allowing $$\V_\text{cmp}\$$ to rise significantly, to nearly $$\V_{DD}\$$ minus the minimum voltage drop over the reference current source.

Likewise, when $$\V_c\$$ < $$\V_\text{ref}\$$, M1's $$\V_\text{GS}\$$ is large, M1 conducts strongly (in triode), and $$\V_\text{cmp}\$$ is close to ground (again, allowing for a small voltage drop across the transistor).

Small-signal analysis would be interesting for the transition point where $$\V_c \approx V_\text{ref}\$$. However, I would suspect that due to various saturation effects, slew rate limitations, and the time it takes to charge/discharge capacitances (not explicitly shown here), that transition point isn't so important. Once the comparator trips, I expect that S1 stays turned on long enough to discharge C so that $$\V_c\$$ ends up well below $$\V_\text{ref}\$$, and we don't spend a lot of time in that nearly-balanced, small-signal regime.

• Hi There, thank for the intuitive response, it makes complete sense now. However would this also be true if the NMOS is working in Sub-threshold saturation, where we can conduct when VGS < Vth? Commented Mar 31 at 19:52
• @soccernismo There is not much merit in talking about sub-threshold for large signal excitations. You aren't at some finely-balanced value between 0 and Vth where the current is exactly right. If Vgs of M1 is less than Vgs of M0 by any non-small-signal value, then M1 is going to carry less current and the output node will rise to a saturated value. Commented Mar 31 at 22:28

I'll be referring to these:

simulate this circuit – Schematic created using CircuitLab

Ideal diodes D1 and D2 limit the $$\I_{REF}\$$ current sources' compliance voltage to a maximum of +12V, so that they more closely emulate the constraints of real-life sources.

M0 is self-biased, meaning that the difference between its gate and source potentials is the transistor's $$\V_{GS(TH)}\$$, which in my circuit is about 2.3V, as measured by VM2.

\begin{aligned} V_G - V_{S0} &= V_{GS(TH)} \\ \\ V_G &= V_{S0} + V_{GS(TH)} \\ \\ &= V_{REF} + V_{GS(TH)} \\ \\ &= 4.0V + 2.3V = +6.3V \\ \\ \end{aligned}

This value for $$\V_G\$$ will remain fixed forever, except for drift and temperature dependencies.

Before I talk further about this, consider that M1 is a sink of current, as represented by I2 here:

simulate this circuit

Effectively we have two current sources in series. This arrangement has huge transimpedance, meaning that even the tiniest imbalance of current between the two sources will result in a large voltage swing at node OUT, looking like this:

It is sufficient for I2 to be only a few microamps different from I1 for $$\V_{OUT}\$$ to swing wildly from one extreme to the other. This is exactly what will happen when MOSFET M1 starts to switch off, which will have the same effect as I2 here dropping below 1mA.

Back to the original circuit, I've replaced C1 with a voltage source, which represents the present capacitor voltage $$\V_C\$$, which I will sweep from 0V upwards. There will be some potential $$\V_{C(TH)}\$$ at which M1 begins to switch off. This will be when M1's $$\V_{GS}\$$ falls below $$\V_{GS(TH)}\$$:

\begin{aligned} V_G - V_{C(TH)} &= V_{GS(TH)} \\ \\ V_{C(TH)} &= V_G - V_{GS(TH)} \\ \\ &= (V_{REF} + V_{GS(TH)}) - V_{GS(TH)} \\ \\ &= V_{REF} \\ \\ &= +4.0V \end{aligned}

In other words, symmetry of the two matched MOSFETs ensures that M1 switches off as the source of M1, $$\V_C\$$, rises above the potential also held by the source of M0, which is $$\V_{REF}\$$. I believe that addresses your question about why M1 amplifies the difference $$\V_C - V_{REF}\$$.

The amount by which this difference is amplified, is related to my previous point regarding two current sources in series. It will be amplified a lot, due to the enormous transimpedance of such an arrangement. Here's a plot of $$\V_{CMP}\$$ as I sweep $$\V_C\$$ upwards from 0V:

Obviously drain potential $$\V_{CMP}\$$ can't ever be below $$\V_C\$$, so it tends to follow $$\V_C\$$ until the point where M1 begins to switch off, and drain current begins to fall. As we predicted, that begins to occur when both MOSFET sources have the same potential, $$\V_C = V_{REF}=+4V\$$.

Then suddenly CMP rises in potential as source $$\I_{REF1}\$$ fights to maintain 1mA of flow.