In the circuit below I am trying to create a "guard ring" for the opamp with high input impedance (~1T Ohm) to avoid femtoampere current leakage. I'd like to ask you guys if I did it right. I researched some documents online but didn't see any specific instructions on it. If there are any errors, I hope everyone can comment.

Besides, if I draw multiple layers, do I need to create a "guard ring" for all layers and how to do that?

Thank you everyone.

Here is my schematic enter image description here

Here is pcb layout with opamp lmc6442

enter image description here enter image description here

And then I add the top solder enter image description here And this is 3d: enter image description here


4 Answers 4


Layout is good. But:

  1. I would make the left side of Rc3 the guard node, so you have a series resistor (Rc3) in there to control resonances.
  2. You should add a cap in series with Rb3, or otherwise your guard node will not be at the same potential as the input. Alternatively, remove Rb3. Either of these measures will stop low frequency current through Rc3, so the guard node will remain at input potential. This is important, or otherwise the diodes become very leaky.

With respect to multilayer: The general principle is the following: When you put yourself into the input node's point of view: Regardless in which direction you look - everything should have the same potential as the input node. So, yes you should add guards to the other layers, if the input is also there. On the bottom layer just proceed as with the top layer and connect the guard traces with exposed vias to the top layer guard node. For inner layers, obviously there is no solder mask, but still you should place a guard ring around the input trace vias in all layers.

  • \$\begingroup\$ Sorry, but I still don't understand why I need to connect an additional capacitor in series with Rb3. Can you explain to me and if I need to add an additional capacitor, what is the reasonable value? \$\endgroup\$ Apr 2 at 13:22
  • \$\begingroup\$ Actually the 2 "Inputs" are Label Net, they will be connected together, so there is only 1 Input and 1 Ouput with no typo here. But thank you, maybe I forgot that C1 is also connected to the input, I think the guard ring area should be expanded to cover C1 as well. \$\endgroup\$ Apr 2 at 13:26
  • \$\begingroup\$ @PhạmSáng before answering your question, maybe please explain the Role of the Rn ourtput resistor divider and the output capacitor. Why do you plan on using output feedback into the non-inverting input? To me it sounds like a certain recipe for oscillation and disaster. Until then, I have to conclude that I don't understand your circuit idea, so will refrain from further suggestions. \$\endgroup\$
    – tobalt
    Apr 3 at 8:06
  • 1
    \$\begingroup\$ It is a cancellation input capacitor technique. To reduce the impact of C_in on the input signal, they use a neutralization circuit including a variable resistor ( R_n) controlled by the positive parameter (λ) which is joined back to the input via C_n. The principle is based on the sum of the current at input and the returned current from C_n equal to the current in C_in, so that it can degrade the value of C_in resulting in insure to maintain the input signal. By adjusting the value of R_n to λ, the input capacitance can be eradicated leading to the independent gain on C_s. \$\endgroup\$ Apr 3 at 8:52
  • \$\begingroup\$ @PhạmSáng Oh ok, sounds plausible.. About your question. Your guarding node, is the node between Rc3 and Rb3, because this is the node on the other side of the diodes. This node MUST be at input potential or otherwise you will get a lot of leakage through the diodes. But as Rb3 is connected to GND, current through it and through Rc3 will bring the voltage away from this potential. You must prevent current flowing through Rb3 (at least at low frequencies), to keep its potential at the input potential. You achieve this either by a small 100pF cap or by simply removing Rb3. \$\endgroup\$
    – tobalt
    Apr 3 at 8:58

You only need guard rings on the bottom as well as the top if you are using a through-hole op-amp.

The guard ring appears to be connected to a relatively low impedance source, which is correct, but it should be at the exact same potential (give or take offset voltage of the op-amp) as the inverting input. You probably also want to minimize the voltage across the input diodes.

Removing the solder mask over the guard trace is also correct.

  • \$\begingroup\$ No, I connect the protection ring to the inverting pin (pin 2) of the opam, pin 3 is the non-inverting pin and is also the pin of the signal with high input impedance that I want to protect. \$\endgroup\$ Apr 2 at 13:20
  • \$\begingroup\$ My protection ring also goes through the diode, or is that still not enough? Can you please suggest me a way to minimize the voltage passing through the input diodes? \$\endgroup\$ Apr 2 at 13:20
  • \$\begingroup\$ Minimizing the voltage across the diodes will minimize the current. But the LMC6442 can have as much as +/- 8mV Vos so that's not so easy. \$\endgroup\$ Apr 2 at 13:27

Surface current leakage is caused by moisture, dust, solder residues, etc. I suggest a wider guard ring, so that a simple dust won't allow a leakage current to appear by passing over the guard ring.

See this example



I also suggest removing the solder mask on the guard ring and inside it, as solder mask can provide a path for surface leakage currents.

See the LMP7721 evaluation board

enter image description here

  • \$\begingroup\$ Sorry but I'm a bit confused with your photo. As I see it, the yellow area available in the pcb photo is the guard ring area, so the red line you circled means the guard ring area should expand to that level right ? \$\endgroup\$ Apr 2 at 13:07
  • \$\begingroup\$ I'm thinking of expanding it to include Rn1_3, Rn2_3, and C1, do you think that's okay? Or can you give me a suggestion on how much expansion is enough ? \$\endgroup\$ Apr 2 at 13:15
  • \$\begingroup\$ Yes, the yellow area on the picture is a protection ring (blue dotted line in the diagram). The red line indicates which part of the schematic it is, as this schematic has two guard rings at different voltages (VREF1 and VREF2). The protection ring protects the high-impedance input, as only this can be affected by leakage currents. Low-impedance outputs don't need it, which is why the guard ring only covers half of C4 and R3. For your design, you need to know what is high impedance (critical) and what is not. \$\endgroup\$
    – Vincent
    Apr 2 at 14:39
  • \$\begingroup\$ So I think I just need cover more half C4 as it is connected to the high-impedance input \$\endgroup\$ Apr 3 at 7:54
  • \$\begingroup\$ Besides, I would to ask how to create a yellow area guard ring like that ? \$\endgroup\$ Apr 3 at 15:45

A guard can only work properly when it completely surrounds the signal to be guarded. And because of this, extending the guard in deeper layers of your printed circuit can absolutely make sense.

Generally, it is most important to identify the primary contributor to any leakage currents when designing a guard ring. In the case of surface mount devices, a single layer guard ring on the signal layer will usually suffice. For through hole components, it is recommended to implement a guard ring on multiple layers.

This article from EDN covers this in detail.


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