# Why does my integrator slowly saturate to negative rail in the following configuration?

So I have the following basic integrator circuit:

The input signal is a 100mVp-p square wave of 50k frequency. In this case I get a stable triangle wave output.

However, when I make the amplitude 500mVp-p keeping everything else same the level around which output oscillates gradually decreases and settles near negative rail. What is the reason for this? I understand that putting a feedback should fix this, but my issue is, I am never letting the cap charge in one direction, so there should be no reason for it to hit the rails.

• Regarding why one waveform saturates in the simulation and another doesn't could you post the waveform code, perhaps there is an error in one. Commented Apr 2 at 18:53
• Is the square wave source exactly a 50% duty cycle? The definition of a square wave in SPICE code is a bit tricky since the rise & fall times need to be considered. Also, take a look at the current waveform on the output of the opamp. You may be asking for to much current at higher voltage drive due to the values of R & C which may cause an offset in the output voltage (|max| and |min| values not the same). Kinder values would be 200 ohms and 10nF.
– qrk
Commented Apr 2 at 23:06

In a perfectly ideal case, it would.

But the simulator you're using appears to model the op-amp as having nonzero input offset and input bias currents. This means that, as far as the op amp is concerned, your input signal may have a small DC bias, which it dutifully integrates over time to produce the drift you see.

This is why real integrators usually include a zeroing resistor across the capacitor, to bleed off this sort of slow output drift. Even using an auto-zero op amp (aka chopper amplifier) won't fully prevent this, though it may allow you to use a larger resistance, thus keeping your integrator closer to an ideal integrator.

• but in this case it should have saturated in the 100mV condition as well right? But it doesn't. Commented Apr 2 at 18:10
• @needbrainscratched Your 500 mV condition was simulated for much longer, giving time for the output to saturate. I suspect the 100 mV one will also saturate (perhaps slower, depending on op-amp characteristics) if you give it enough time. Commented Apr 2 at 18:20
• More likely an effect of the bias currents, moreso than input offset voltage. Commented Apr 2 at 18:55

Why does my integrator slowly saturate to negative rail in the following configuration?

No op-amp is perfect. All op-amps have some offset voltage and bias current. These will eventually saturate an integrator unless there is a resistor in parallel with the capacitor.

Like Hearth and Math said, the opamp has bias current that gets integrated in the long term. Putting a high value resistor across the cap will help. Another trick is to put a resistor in series with the non-inverting input as a means of compensation. Not a great solution, but it helps. A complex way to deal with this problem is to use another op-amp and "servo" out the error with a large time constant - much larger than you integration period.

You said it yourself. It is an integrator. It means that a DC signal in input implies a slope in output, the closer to 0V is the input, the slower the slope of the output signal. It means that you may have a negative DC voltage very close to 0. This is where you face the realities of ideal integrator and practical integrator. Anyways, you can give a glance at this link to have an idea about how you could tackle/limit this issue : https://www.electronics-tutorial.net/analog-integrated-circuits/op-amp-integrator/practical-integrator/ They use a resistor in parallel with the integrating capacitor. It allows the capacitor to not keep its charge when there is not supposed to be any. I let you find the value of this resistor in parallel in the same link.