3
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Background

Source claims that this MOSFET-based charge pump circuit should work. The schematic looks logical and I was able to reason my way through its expected behaviour. I tried simulating the circuit in LTspice but that did not yield the expected results.

As a sanity check I also built the circuit in Falstad, which, to my surprise (and confusion), works in line with my original expectations. All nodes behave exactly as I expect them to.

In LTspice I tried simulating with real board-level models (VDMOS) as well as monolithic MOSFETS. I tried replacing the NMOS transistors with NPN BJTs. Nothing works apart from running the simulation with idealised, switch-based models of the MOSFETS.

Original Schematic

Original Schematic

Expected Operation

Negative Pulse

Behaviour on Positive Pulse

Positive Pulse

Behaviour on Positive Pulse

Simulations

Falstad

Works as expected:

Link to Simulation Falstad Simulation

LTspice

Simulation realised with VDMOS models does not work at all:

Version 4
SHEET 1 2368 1416
WIRE 48 -96 -32 -96
WIRE 320 -96 48 -96
WIRE 48 -80 48 -96
WIRE 320 -64 320 -96
WIRE 208 16 176 16
WIRE 272 16 208 16
WIRE 48 32 48 0
WIRE 208 64 208 16
WIRE 224 64 208 64
WIRE 320 64 320 32
WIRE 320 64 304 64
WIRE 48 176 0 176
WIRE 112 176 48 176
WIRE 240 176 112 176
WIRE 320 176 320 64
WIRE 320 176 304 176
WIRE 352 176 320 176
WIRE 512 176 448 176
WIRE 576 176 512 176
WIRE 640 176 576 176
WIRE 688 176 640 176
WIRE 48 192 48 176
WIRE 576 192 576 176
WIRE 640 192 640 176
WIRE 512 208 512 176
WIRE 208 240 208 64
WIRE 320 288 304 288
WIRE 576 288 576 256
WIRE 640 288 640 272
WIRE 48 304 48 272
WIRE 304 320 304 288
WIRE 304 320 256 320
WIRE 432 320 432 224
WIRE 432 320 304 320
WIRE 512 320 512 288
WIRE 512 320 432 320
WIRE 208 368 208 336
WIRE 432 368 432 320
WIRE 432 384 432 368
WIRE 320 416 304 416
WIRE 112 448 112 176
WIRE 304 448 304 416
WIRE 304 448 112 448
WIRE 384 448 304 448
WIRE 432 496 432 464
FLAG 48 304 0
FLAG 688 176 OUT
IOPIN 688 176 Out
FLAG 576 288 0
FLAG 640 288 0
FLAG 48 32 0
FLAG 208 368 0
FLAG 432 496 0
FLAG -32 -96 IN
IOPIN -32 -96 In
FLAG 320 288 G3
IOPIN 320 288 Out
FLAG 320 416 G4
IOPIN 320 416 Out
FLAG 0 176 PULSE
IOPIN 0 176 In
FLAG 176 16 G1
IOPIN 176 16 Out
FLAG -96 1152 0
FLAG -96 1056 0
FLAG -48 1136 0
FLAG -96 896 0
FLAG -96 800 0
FLAG -48 880 0
SYMBOL voltage 48 176 R0
WINDOW 3 -115 -20 Left 1
WINDOW 39 -42 69 Right 2
WINDOW 0 -46 51 Right 2
WINDOW 123 0 0 Left 0
SYMATTR Value PULSE(0 {V} 0 {trise} {tfall} {ton} {period})
SYMATTR SpiceLine Rser={Rs}
SYMATTR InstName V2
SYMBOL voltage 48 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 -41 77 Right 2
WINDOW 0 -45 36 Right 2
WINDOW 3 -42 56 Right 2
SYMATTR SpiceLine Rser={Rs}
SYMATTR InstName V1
SYMATTR Value {V}
SYMBOL res 624 176 R0
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL res 528 304 R180
WINDOW 0 31 76 Left 2
WINDOW 3 31 40 Left 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 320 48 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 27 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL pmos 272 -64 R0
WINDOW 3 55 57 Left 2
SYMATTR InstName M1
SYMBOL pmos 352 224 R270
WINDOW 0 86 5 VRight 2
WINDOW 3 65 2 VRight 2
SYMATTR InstName M2
SYMBOL nmos 256 240 M0
WINDOW 3 56 51 Left 2
SYMATTR InstName M3
SYMBOL nmos 384 368 R0
WINDOW 3 56 55 Left 2
SYMATTR InstName M4
SYMBOL polcap 304 160 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10�
SYMATTR Description Capacitor
SYMATTR Type cap
SYMBOL polcap 560 192 R0
SYMATTR InstName C2
SYMATTR Value 10�
SYMATTR Description Capacitor
SYMATTR Type cap
SYMBOL nmos -48 1056 M0
WINDOW 3 -16 126 Left 2
WINDOW 0 33 -33 Left 2
SYMATTR Value AONS32100
SYMATTR InstName MN
SYMBOL polcap 576 -48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 10�
SYMATTR Description Capacitor
SYMATTR Type cap
SYMATTR SpiceLine V=63 Irms=1.22 Rser=0.15 Lser=2n
SYMBOL polcap 608 -64 R0
SYMATTR InstName C4
SYMATTR Value 10�
SYMATTR Description Capacitor
SYMATTR Type cap
SYMATTR SpiceLine V=50 Irms=48m Rser=0.6 Lser=3.7n mfg="W�rth Elektronik" pn="860130673001 WCAP-ATET 6.3x11" type="Al electrolytic"
SYMBOL pmos -48 800 M0
WINDOW 0 33 -31 Left 2
WINDOW 3 -14 127 Left 2
SYMATTR InstName MP
SYMATTR Value SQ4435EY
TEXT 448 1008 Left 2 ;.model NMOS VDMOS(\n+Kp=225 Rs=50u Rd=200u Rg=1.4 \n+Vto=1.67 VtoTc=-2.2m Bex=-1.15 \n+mtriode=2 Ksubthres=0.1 Lambda=0.063 \n+Cgdmax=5963f Cgdmin=1207f Cgs=13800f \n+tt=36n A=0.49 Is=1.61E-10 \n+N=1.035 Rb=1u Eg=1.03 \n+Trb1=2.5m M=0.503 Vj=0.94 \n+Cjo=2580.0pF mfg=AOS Vds=25 \n+Ron=0.6m Qg=115n)
TEXT -8 768 Left 2 !.model PMOS VDMOS(\n+pchan Kp=11.219 Rs=0.0001 Rd=0.0013 \n+Rg=4.5 Vto=-2.26 lambda=0.01 Cgdmax=1890p \n+Cgdmin=250p Cgs=1400p TT=65n \n+Is=2.06E-13 N=0.954 Rb=0.005664 \n+M=0.937 VJ=2.31 Cjo=500.73pF \n+mfg=Vishay Vds=-30 \n+Ron=0.018 Qg=38.3n)
TEXT -8 1008 Left 2 !.model NMOS VDMOS(\n+Kp=225 Rs=50u Rd=200u Rg=1.4 \n+Vto=1.67 VtoTc=-2.2m Bex=-1.15 \n+mtriode=2 Ksubthres=0.1 Lambda=0.063 \n+Cgdmax=5963p Cgdmin=1207p Cgs=13800p \n+tt=36n A=0.49 Is=1.61E-10 \n+N=1.035 Rb=1u Eg=1.03 \n+Trb1=2.5m M=0.503 Vj=0.94 \n+Cjo=2580.0pF mfg=AOS Vds=25 \n+Ron=0.6m Qg=115n)
TEXT 448 768 Left 2 ;.model PMOS VDMOS(\n+pchan Kp=11.219 Rs=0.0001 Rd=0.0013 \n+Rg=4.5 Vto=-2.26 lambda=0.01 Cgdmax=1890f \n+Cgdmin=250f Cgs=1400f TT=65n \n+Is=2.06E-13 N=0.954 Rb=0.005664 \n+M=0.937 VJ=2.31 Cjo=500.73pF \n+mfg=Vishay Vds=-30 \n+Ron=0.018 Qg=38.3n)
TEXT 520 -96 Left 2 ;Non-Ideal Caps
TEXT -8 960 Left 3 ;NMOS Models
TEXT -8 720 Left 3 ;PMOS Models
TEXT 448 984 Left 1 ;Reduced Capacitance
TEXT 448 744 Left 1 ;Reduced Capacitance
TEXT -8 744 Left 1 ;Original Capacitance
TEXT -8 984 Left 1 ;Original Capacitance
TEXT 568 648 Left 2 !.tran {10*period} startup
TEXT 568 624 Left 2 !.options nomarch
TEXT 568 376 Left 2 !.param V=5 Rs=1
TEXT 568 400 Left 2 !.param freq = 5k
TEXT 568 536 Left 2 !.param ton = {period / 2 - trise}
TEXT 568 512 Left 2 !.param period = {1/freq}
TEXT 568 424 Left 2 !.param trise = 10n
TEXT 568 448 Left 2 !.param tfall = trise
TEXT 568 560 Left 2 !.param toff = {period / 2 - tfall}
TEXT 568 352 Left 2 ;Inputs
TEXT 568 488 Left 2 ;Calculations
TEXT 568 600 Left 2 ;Simulation

LTspice Simulation

Question

What critical parameter am I missing that results in a non-working circuit in LTspice?

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  • \$\begingroup\$ Replace (temporarily) all MOSFETs with diodes pointing in the same direction as their respective MOSFET body diodes and see what you get. If looking OK (a stable output) try introducing one MOSFET at a time. \$\endgroup\$
    – Andy aka
    Commented Apr 4 at 17:36

1 Answer 1

1
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This is your original simulation file:

enter image description here

In your simulation, the G3 voltage rises slowly when the pulse is low (0). This is because the total capacitance present at that node is the sum of M3's gate-source capacitance and M4's capacitance which is a combination of the output capacitance (Cgd) and the parasitic body diode capacitance (Cjo):

enter image description here

Having a slow G3 voltage is enough to get the circuit to fail.

Even your Reduced Capacitance models can't work because you left Cjo unchanged (high):

enter image description here

So if you use MOSFETs with lower output and parasitic diode capacitance the circuit will work as expected.

As proof, here are the waveforms of the same circuit with 2N7002 (NMOS) and BSS84 (PMOS):

enter image description here

PS: Sorry, I need to watch tonight's Liverpool match so I can't write a more detailed answer. But I think the explanation above should be enough for you to get the idea.

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  • \$\begingroup\$ Hmm. I knew that capacitance had to be the culprit... I was on the right track but was not aware of the Cjo parameter. Is it common to have such high Cjo for very low Ron MOSFETS? \$\endgroup\$
    – pfabri
    Commented Apr 5 at 14:20
  • \$\begingroup\$ @pfabri I don't know but Cjo normally depends on other parasitic capacitances of the MOSFET for non-zero drain-source voltages (Vds), and is almost equal to Coss when Vds is zero. If you look at the model parameters, you'll see that there's no Coss or a similar thing. Instead, all are combined into Cjo. Lower Ron is usually achieved with channel dimensions (e.g. larger die) and as a result, a silicon MOSFET may have higher Cjo since C is proportional to A (surface area) and inversely proportional to d (distance between surfaces). \$\endgroup\$ Commented Apr 5 at 15:30
  • \$\begingroup\$ Very clear, thanks! \$\endgroup\$
    – pfabri
    Commented Apr 8 at 13:35

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