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I'm trying to simulate a verilog module that uses the "lpm_add_sub" module to provide an adder with a separate carry in (for some reason Quartus II doesn't recognise that a+b+c where c is a single bit can be implemented in a single adder and synthesizes two adders for it). However when I try to start the simulation in ModelSim, I get the following messages:

vsim -L altera_ver -L altera_mf_ver -L cycloneiv_ver -L cycloneive_ver -L lpm_ver -voptargs=+acc work.rotation_sensor
# vsim -L altera_ver -L altera_mf_ver -L cycloneiv_ver -L cycloneive_ver -L lpm_ver -voptargs=+acc work.rotation_sensor 
# Loading work.rotation_sensor
# Loading work.bitcounter
# Loading lpm_ver.lpm_add_sub
# ** Error: (vsim-3584) C:/Development/ican/IcanFinal2/rotation_sensor.v(119): Module parameter 'LPM_DIRECTION' not found for override.
# 
#         Region: /rotation_sensor/bitcounter/genblk1
# ** Error: (vsim-3584) C:/Development/ican/IcanFinal2/rotation_sensor.v(119): Module parameter 'LPM_REPRESENTATION' not found for override.
# 
#         Region: /rotation_sensor/bitcounter/genblk1
# ** Error: (vsim-3584) C:/Development/ican/IcanFinal2/rotation_sensor.v(119): Module parameter 'LPM_WIDTH' not found for override.
# 
#         Region: /rotation_sensor/bitcounter/genblk1
# Error loading design

Any ideas what I'm doing wrong? The line of code causing the error is this:

        lpm_add_sub #(.LPM_DIRECTION("ADD"), .LPM_WIDTH(SUBRESULTSIZE), .LPM_REPRESENTATION("UNSIGNED")) a (
            .dataa(tophalf_count),
            .datab(bottomhalf_count),
            .cin(bits[INPUTWIDTH-1]),
            .result(add_out[SUBRESULTSIZE-1:0]),
            .cout(add_out[SUBRESULTSIZE]));
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According to Altera's knowledge base, it's a bug in their simulation library, which incorrectly has the parameter names defined only in lower case (it should, apparently, be able to accept either).

http://www.altera.co.uk/support/kdb/solutions/rd04192000_5867.html

Searching directly for the error message didn't turn it up, because the text of the error message appears to have changed since they added the description of the problem to their knowledge base.

Fortunately, for synthesis the lower case names are accepted just as the upper case ones (as used in the documentation) are.

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