# Analysis of the below op-amp circuit and its waveform

What will be the output voltage and capacitor voltage waveform for this problem?

[The approach I tried --> When the diode is ON, the negative feedback is complete and voltage of inverting terminal is 0V (due to ideal op-amp + virtual short). As a result, the output resistor is shorted and Vo should be 0 in that case. But I am not sure about other scenarios how the circuit will behave]

Any help here will be appreciated. Thanks

• Assuming an ideal op amp, the output will stay 1 diode drop above ground when the current is going right to left through the capacitor. If the current is going left to right through the capacitor, the op amp will go full negative, since there is no feedback (diode not conducting), in which case you have only the C and the R effectively in the circuit. Commented Apr 9 at 16:18
• Please clarify your specific problem or provide additional details to highlight exactly what you need. As it's currently written, it's hard to tell exactly what you're asking.
– Community Bot
Commented Apr 9 at 16:27
• @CristobolPolychronopolis, can you explain in detail with the waveforms? I agree with you. For the case of current going R to L, assuming ideal diode, Vo will be zero. For current going L-R, diode will be OFF and it will be an RC circuit. But to draw the waveforms, I am unable to figure out the exact instances where these two cases will occur. Commented Apr 9 at 17:47
• May I know the value of C Commented Apr 9 at 17:59
• @Hari R and C are variables. Can assume any value if needed, but I guess it shouldn't matter as we just require waveforms. Commented Apr 9 at 18:32

It's difficult to know what answer the author of this question expects, because the answer will depend heavily on the values of R and C. If the period $$\T\$$ of the input waveform is significantly smaller than the time constant $$\\tau=RC\$$, then this circuit performs "DC restoration", shifting the waveform upwards until its troughs (the "valleys", or lowest points) just touch 0V. I'll explain why in a moment, but for now a simulation will demonstrate this behaviour:

simulate this circuit – Schematic created using CircuitLab

The response to the input sinusoid $$\V_{IN}=1+2sin(\omega t)\$$ (blue) is $$\V_{OUT1}=2+2sin(\omega t)\$$ (orange):

I've chosen R1 and C1 such that $$\R_1C_1 >> \frac{1}{\omega}\$$, which means that $$\V_{IN}\$$ changes much faster than C1 can charge/discharge.

Any voltage $$\V_{C1}\$$ across C1 is an "offset" to $$\V_{IN}\$$, so that the potential $$\V_Q\$$ (at the op-amp's inverting input) is $$\V_Q = V_{IN}+V_{C1}\$$. Initially, C1 has no charge, and no voltage across it, and $$\V_Q=V_{IN}\$$, but from the above graph we can infer that C1 seems to develop a charge, causing the output to be offset upwards by exactly 1V. To understand this, let's examine $$\V_P\$$, the op-amp output:

When $$\V_Q > 0\$$ the op-amp output saturates to $$\V_P=-12V\$$, but the diode is permanently reverse-biased, and $$\V_P\$$ can have no influence on $$\V_Q\$$. The op-amp can be disregarded.

When $$\V_Q < 0\$$, 100% negative feedback causes the op-amp to behave as a voltage follower (don't forget that the diode will develop 0.7V when it's conducting, and this can be seen above as an offset of 0.7V). During these intervals of diode conduction, the op-amp charges C1 via the diode, causing $$\V_Q\$$ to rise until it reaches zero.

During each cycle, then, if $$\V_Q\$$ ever becomes negative, the op-amp "follows", and C1 charges to whatever voltage is necessary to make $$\V_Q=0\$$ again, resulting in a "permanent" offset to $$\V_{IN}\$$. In other words, C1 will always develop exactly the right charge to cause $$\V_Q \ge 0\$$, and C1 gets "topped up" during each negative excursion of $$\V_Q\$$.

Of course our output is $$\V_{OUT}=V_Q\$$, and so it becomes the "shifted upwards" version of the input.

I believe this is what the author intended, for you to draw the graph of $$\V_{OUT}=2+2sin(\omega t)\$$, but this could be wrong. Using "reasonable" component values of microfarads and kilohms for C and R would have very different results for an input signal of 1 radian per second, since C1 would discharge long before a cycle has completed:

simulate this circuit

Lastly, I will point out that the use of the op-amp here is really just an idealised version of the much simpler passive DC restorer:

simulate this circuit

If D1 above were not ideal (which is always the case, of course), its 0.7V drop would ruin the behaviour of having signal lows sit exactly on the zero-volt level. The op-amp is employed to obtain closer to "ideal diode" behaviour.

• Thanks a lot for such a detailed explanation (including the case when RC is comparable to T). Commented Apr 10 at 12:32

The original problem didn't specify the details about R & C, but upon assuming the condition that time-constant RC >> T, the capacitor C won't really be able to charge/discharge through R and will eventually assume a fixed voltage (1V in this case). Subsequently the output will be clamped to Vo = Vin + Vc = (2 + 2sinwt).

P.S. - This indeed is a standard active clamper circuit. I was able to find a great youtube video explaining the complete operation of the same - Active Clamper Circuit Explained

Below is the hand-drawn waveform for the problem (RC >> T assumed)

# Generalized voltage divider configuration

Since the question of the so-called “DC restoration circuit” was raised here, I will share my finding that there is no difference between this circuit and the diode rectifier. They are the same circuit except that the output voltage is taken from different places. This phenomenon can also be observed in other well-known base voltage divider configurations; so I will summarize it through three typical examples.

# Basic idea

In this configuration, three devices - a voltage source and two passive elements, are connected in a loop. The current in the circuit is the same, and the input voltage is distributed between the two elements depending on their characteristics. One, the other, or both voltage drops can be used as output voltages. It depends on which point we use as ground (in this circuit of three devices, only two of them can be grounded).

# Diode-capacitor circuit

Let's begin with the OP's circuit where an AC voltage source, diode and capacitor are connected in a loop. I have removed the non-essential elements for understanding the idea - the "lifting" 1 V voltage source and the load.

## 2-output RD circuit

In this configuration, both capacitor and diode are grounded, and the complementary voltage drops across them can be used as outputs.

simulate this circuit – Schematic created using CircuitLab

## Diode rectifier

Here the capacitor is grounded and the diode is "floating". The voltage across the capacitor is constant, and can be used as an output voltage.

simulate this circuit

## DC restoration circuit

Unloaded: Conversely, in the OP's circuit, the diode is grounded and the capacitor is "floating". The voltage across the diode is a sum of the input AC voltage and the "shifting" voltage across the capacitor; so the input voltage is "lifted" with 10 V, and appears at the output.

simulate this circuit

Loaded: Note that almost all the time, the diode is backward biased.

simulate this circuit

To see the short current spikes, I have added a 1MΩ load.

Low input voltage: The input voltage above was 10 V., and only 0.7 V was lost across the forward-biased diode. But if the input voltage is too small, e.g. 1 V, almost all the voltage will be lost in the diode.

simulate this circuit

As you can see, the input and output voltage curves almost match (and should be offset by 1 V).

Compensated: We can solve this problem by adding the same 0.7 V voltage with another voltage source VA (a properly supplied op-amp like in the OP's schematic) in series. As a result of this clever trick, the undesired 0.7 V diode voltage drop is compensated, and the effective voltage across the network is 0 V (virtual short).

simulate this circuit

Now the output voltage curve is lifted with 1 V above the input voltage curve.

# Resistor-capacitor circuit

The same phenomenon can be seen in the humble RC circuit where an AC voltage source, resistor and capacitor are connected in a loop.

## 2-output RC circuit

In the general case, both resistor and capacitor can be grounded, and the complementary voltage drops across them can be used as outputs.

simulate this circuit

## Integrating circuit

First, the capacitor can be grounded and the resistor "floating". The voltage across the capacitor is an integral of the input voltage, and can be used as an output.

simulate this circuit

## Differentiating circuit

Then, the resistor can be grounded and the capacitor "floating". Now, the voltage across the resistor is a differential of the input voltage, and also can be used as an output.

simulate this circuit

So, there is no difference between the integrating and differentiating circuits; they are the same.

# Attenuating circuit

Finally, let's see this phenomenon in the simplest voltage divider circuit where the voltage source, and two resistors are connected in a loop.

simulate this circuit

## Voltage divider 1

First, R2 can be grounded, and R1 "floating". The (output) voltage across R2 is a proportional part of the input voltage, and can be used as an output.

simulate this circuit

## Voltage divider 2

Then, R1 can be grounded, and R2 "floating". The voltage across R1 is the inverse proportional part of the input voltage, and also can be used as an output.

simulate this circuit

So, there is no difference between the two circuits with swapped resistors; they are the same voltage divider configuration.

If C is a "high" value (1 F, nobody fixes it) then the output is sinusoidal.
DC value is V1, variable value is V2 (1 Vpeak, w=1 or $$\f=1/(2*pi)\$$ )

Update: V2 = 2 Vpeak ... Low side of sinus "locked" on zero Volt. The transient may be "long".
V1 does not matter at "steady state" waveform.
The average voltage is equal to the "peak" voltage ... that is to say "2 Volt".

• This says nothing about how to handle the hard part of the question, which is the diode, needlessly makes assumptions about the size of the circuit element, and ignores the fact that the figure specifies the sinusoid at twice the voltage you do (which puts your answer in the uninteresting region for the diode). Commented Apr 9 at 19:27
• The V2 amplitude and frequency are incorrect. Commented Apr 9 at 21:45
• @AnalogKid OK for the amplitude, not for frequency (it is only a label). The graph is ok. The low side of the sinusoid is locked on the zero Volt at output. I update my waveforms. Commented Apr 10 at 6:07
• @ScottSeidman the question is only "draw ..." and asks for the averaged voltage ... which is a "steady" state question ... Commented Apr 10 at 6:20
• @ScottSeidman And the amplitude of the sinusoid does not "really" matter ... Commented Apr 10 at 7:13