# Call a Finite State Machine in VHDL

I need to read data from a SRAM in one step (something like READ_RAM(addr) that returns the value stored in the SRAM at the "addr" address). Is it possible create a function/procedure that integrates a Finite State Machine?

A procedure, on the other hand, can contain sequential statements, but when they do they are mostly used for testbenches using wait statements, which are not synthesizable.
• There are many ways to do this. If your latency is constant, after starting the read then have a counter count up to X (or X-1), and when it reaches this value grab the data output by your SRAM controller. If the latency is not constant, the controller must have some kind of validdata signal that you can poll. – apalopohapa May 29 '13 at 17:29
• You can use a FSM (coded as a process). When you are waiting for MemReady you enter a state, call it something like st_waitingForMemReady, and to get out of that state you check the value of MemReady. Something like if MemReady = '1' then next_state <= st_doneReading; end if; – apalopohapa May 29 '13 at 17:40