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I am getting started with the Virtex VC709 FPGA board, moving on from a much simpler Digilent FPGA development board. I get critical warnings trying to configure a single ended 100MHz clock from the 200MHz differential clock on the board, using the Xilinx clocking wizard.

Below is the top level hardware design for testing the board; it should instantiate a FDCE flip flop and an output buffer to an on-board LED. Along with input buffers for the push buttons on the board.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Top_level is
  Port (clk_in1_p : in std_logic;
        clk_in1_n : in std_logic;
        rst_i : in std_logic;
        button_south_i : in std_logic;
        led0_o : out std_logic        
       );
end Top_level;

architecture Behavioral of Top_level is

signal clk_100mhz : std_logic;
signal ff_out : std_logic;

signal rst : std_logic;

component clk_wiz_0
port
 (-- Clock in ports
  -- Clock out ports
  clk_out1          : out    std_logic;
  clk_in1_p         : in     std_logic;
  clk_in1_n         : in     std_logic
 );
end component;

begin

rst <= rst_i when rising_edge(clk_100mhz);

clock_gen_100mhz : clk_wiz_0
   port map ( 
  -- Clock out ports  
   clk_out1 => clk_100mhz,
   -- Clock in ports
   clk_in1_p => clk_in1_p,
   clk_in1_n => clk_in1_n
 );
 
ff_logic : Process(clk_100mhz, rst, button_south_i)

begin

if (rst = '1') then
    ff_out <= '0';
    
elsif (rising_edge(clk_100mhz)) then
    ff_out <= button_south_i;

end if;

end Process;

led0_o <= ff_out;

end Behavioral;

And below is the constraints file.

# Clocks
create_clock -name clk_ref_200mhz -period 5 [get_ports clk_in1_p]

set_property IOSTANDARD DIFF_SSTL15 [get_ports clk_in1_p]
set_property PACKAGE_PIN H19 [get_ports clk_in1_p]

set_property IOSTANDARD DIFF_SSTL15 [get_ports clk_in1_n]
set_property PACKAGE_PIN G18 [get_ports clk_in1_n]

create_generated_clock -name clk_100mhz -source [get_pins clock_gen_100mhz/clk_in1_p] -divide_by 2 [get_pins clock_gen_100mhz/clk_out1]

# Reset button
set_property PACKAGE_PIN AV39 [get_ports rst_i]
set_property IOSTANDARD LVCMOS18 [get_ports rst_i]

# Start button
set_property PACKAGE_PIN AP40 [get_ports button_south_i]
set_property IOSTANDARD LVCMOS18 [get_ports button_south_i]

# LED 0
set_property PACKAGE_PIN AM39 [get_ports led0_o]
set_property IOSTANDARD LVCMOS18 [get_ports led0_o]

# Board voltage config
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]

The Vivado tools generate the following critical warnings from synthesis.

Critical warnings image

It seems like the tools are trying to use the constraints from the clock wizard IP constraints file? How is this the clocking supposed to be done on the VC709? Do you copy the clocking wizard IP constraints into the main constraints file maybe?

EDIT

I have selected the system differential clock as the input clock.

Clocking wizard image 1

Clocking wizard image 2

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  • 1
    \$\begingroup\$ In the clocking wizard tab "Clocking options" - what did you specify in the "Source" column in the "Input clock information" table? If it's any variation of "... clock capable pin" then the clocking wizards instantiates input buffers, and the constraints from the wizard are propagated up to the clock input port. You can't define your own constraints in this case. \$\endgroup\$
    – Vlad
    Commented Apr 15 at 13:54
  • \$\begingroup\$ @Vlad I have edited my question with an image of the clocking wizard. I have also tried changing the clock source to custom instead of system diff clock but same warnings. \$\endgroup\$
    – David777
    Commented Apr 16 at 7:35
  • 1
    \$\begingroup\$ You've used vivado convenience feature - board definitions. The port selected in the "board" tab will take all the constraints from the board definition files in xilinx store, and you do not need to write your own constraints at all. If you truly need custom constraints - not only you need to set "custom" on the "board" tab, you must go back to "clocking options" tab to change the source to 'global buffer' or 'no buffer' - it will be enabled (currently it is disabled because using board description overrides that). In case of 'no buffer' you have to instantiate buffer explicitly in your design \$\endgroup\$
    – Vlad
    Commented Apr 16 at 8:15
  • \$\begingroup\$ @Vlad I removed the clock constraints from my constraints file and the critical warnings are now gone. Thank you! So the synthesis tools are using the clocking constraints generated by the clock wizard instead. \$\endgroup\$
    – David777
    Commented Apr 16 at 8:46

1 Answer 1

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+100
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When using PLLs/MMCMs with modern FPGA toolchains, the tools are generally smart enough to figure out all of the derived constraints. So you shouldn't need to specify any sort of generated clock constraints, the tools will figure that out, and it looks like that's the source of one of your critical warnings.

The generated constraints will usually be computed based off of the input clock constraint and requested PLL configuration. I usually just use the bare PLL/MMCM primitive instead of the clocking wizard, so in my case I only need to add a constraint for the input clock. But some IP cores will add constraints for external clock inputs based on the configuration - for example, IIRC the CMAC cores on US/US+ will add a constraint for the reference clock when generated with the GTYs in the core. It looks like your other critical warning is a conflict between the constraint you specified and one generated automatically by the clocking wizard.

So, delete or comment out both of the clock constraints and you should be good to go. Or alternatively, there might be an option in the clock wizard to disable generation of the constraint for the input clock, in which case you can keep that one and remove the generated clock constraint.

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