I'm using a SRAM in order to store a frame that I have to display on screen with the VGA interface. I need to read the pixel value from the SRAM and then send it to the VGA monitor. I have created a SRAM Controller but it takes some clock cycles before the data are available. I don't know how to access to the RAM without exit from the Pixel process.

Here's a simplified part of the code:

process (CLK_25MHZ)
    if (CLK_25MHZ'event and CLK_25MHZ = '1') then
        if (ACTIVE_VIDEO) then
            -- This part is repeated for every pixel and I can't exit from this part
            -- until I have sent the pixel data. If I exit this pixel is lost.
            -- I need something like this:
            addr <= CALCULATE_ADDRESS();
            VGA_RGB <= READ_RAM(addr);
            VGA_RGB <= "000000000000";      
        end if;
        -- Here there are the signals timings.
    end if;
end process;
  • 1
    \$\begingroup\$ How many cycles does your SRAM controller take to read? Can it be pipelined? Does it run at a higher frequency? \$\endgroup\$ – pjc50 May 29 '13 at 18:50
  • \$\begingroup\$ Please include your declaration of CALCULATE_ADDRESS. \$\endgroup\$ – Brian Carlton May 29 '13 at 18:56
  • \$\begingroup\$ In order to generate a 640x480x60Hz display, you need to produce pixels at a 25 MHz rate. If your SRAM can't deliver fresh data on every clock cycle, it doesn't have the bandwidth required to support this application. \$\endgroup\$ – Dave Tweed May 29 '13 at 18:57
  • \$\begingroup\$ @pjc50. The controller run at an higher frequency and now need 5 clock cycles to read the RAM. I will optimize the controller and as soon as possible use a faster RAM but for now it is slower than what the VGA requires. I think that an idea can be starts to read data for a pixel in the previous pixel. Is it correct? \$\endgroup\$ – Oceanic815 May 29 '13 at 18:57
  • \$\begingroup\$ @Brian Carlton. I have inserted the CALCULATE_ADDRESS row only for make sense at the next line. I haven't already wrote this part but I haven't problem for this. \$\endgroup\$ – Oceanic815 May 29 '13 at 19:00

I think what you are trying to achieve is possible but you need to tweak your design and think about how you will overcome the limitations of the read speed of your RAM.

Regarding the speed, I think the best thing you can do is read data out and store it during the blanking periods of the video, this can be done using a FIFO, the size of which will be determined by the difference in the amount of data you need during the active video period and the amount of data that can be provided by the RAM in that time, hopefully, it will only be a few lines.

As for the read delay, if you were to implement the FIFO, this would be reduced, if you didn't want to do that then you need to replicate the ACTIVE_VIDEO signal but offset it by 5 clocks and use the delayed signal in your IF statement. This will sync when the data arrives with when you need it, as all the data will be delayed by the same amount, the video data will still be aligned.

hope this helps,


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