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I'm trying to design a circuit where if an error signal goes high, the circuit opens and doesn't close again even if the error signal goes low again until a reset button is pushed. My idea was to put two MOSFETs in series as this (although I'm not restricted to this structure):
enter image description here

This way, when the top MOSFET opens, the reset circuit would open the bottom MOSFET and will not close it again until the error signal goes low and the button in pushed. I've been trying various configurations for the reset circuit but I haven't been able to find one that works correctly.

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2 Answers 2

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If your load is tied to 0 volts/GND then it's best to use a high-side switch but, trying to implement this with an N-channel MOSFET is probably more hassle than what it's worth so, instead, use a high-side P-channel MOSFET with the output to the load from the MOSFET drain. To deactivate the MOSFET you need a resistor between gate and source of a few tens of kΩ and, you need another transistor to activate the PMOS: -

enter image description here

Image from P-Channel MOSFET high side switch.

So, all that remains is the logic that drives this circuit and, I would recommend using a D-type flip-flop with the output feeding T1 (via a 10 kΩ resistor) from \$\overline{Q}\$ on the flip flop. Use the \$CLK\$ input for your trigger and tie the \$D\$ input to Vcc. Pick a flip-flop that has a reset line for the reset button.

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  • \$\begingroup\$ Any reason to prefer a D-type flip-flop to an SR or S'R' latch? \$\endgroup\$ Apr 14 at 13:28
  • \$\begingroup\$ @MathKeepsMeBusy I know I can get one with a clear pin but, any of several types would be OK. \$\endgroup\$
    – Andy aka
    Apr 14 at 15:03
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even if the error signal goes low again

So the error signal's high state is latched. IOW it is setting a flipflop. To reset the flipflop, a Reset button is pushed. However, the Reset function will not work if the Error signal still is high. So this is a set-reset flipflop with the set input overriding the reset input. If all of that is correct, then . . .

Your 2-transistor AND gate approach is ok except that it does not have any feedback so there is no latch function. Doing this plus switching power to a load is best done with three transistors - two for the latch and one for the load. Another approach is an IC flipflop plus an external load-switch transistor.

Another issue is that you show what I'm guessing are n-channel FETs. In order for the upper FET (reference designators - !) to turn on, its gate voltage has to be several volts greater than its source. Andy's circuit solves this with a p-channel FET for the load switch, but you still need a latch.

UPDATE:

enter image description here

Here is a first pass at a schematic. I got it down to only two transistors, but at a cost. Because Q2 is part of both the latch circuit and the power switch to the load, the external load is part of the latch circuit, and a very small current goes through the load in the off state. This is the holding current for that latch state.

When Error is high, the D1 cathode is about 0.6 V below Vcc. This is high enough to turn off Q2, which pulls the Q1 gate low, which pulls the Q1 drain high, which holds Q2 in the off state when Error returns low.

SW1 pulls the Q1 gate high, turning it off. R1 then turns on Q2, powering the load. The Q2 drain also pulls the Q1 gate high, holding it off.

You don't state a preference for the power-up condition, so C1 assures that the circuit powers up in the "load off" state if Error is low. It should be 0.1 uF.

You also don't state the load current, so I threw in a typical p-channel power MOSFET from my design library. This can be changed to any appropriate type. Also, Q1 can be a small-signal type.

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  • \$\begingroup\$ See the UPDATE. \$\endgroup\$
    – AnalogKid
    Apr 14 at 17:24

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