Use a full ground and power plane. Bypass caps are limited by inductance, which is mostly determined by package size, traces, and vias. So pick the smallest package size that you can work with, then go for the largest capacitance that doesn't break your budget. If you need more bypassing, go up a package size or two and get the biggest capacitance in that package. When connecting the cap to the ground/power planes, use two vias on either side of each pad; vias + cap will look kinda like an H.
Splitting the planes can help isolate the analog and digital sections. Never cross a split plane with a signal trace!!! Keep signals away from the edge of the board. Keep signals at least 2x trace width apart to prevent crosstalk (simulations are helpful here). Keep signals 5x trace width away from highly noisy signals (i.e. clocks) or extremely sensitive signals (i.e. analog inputs). Use grounded guard traces around noisy/sensitive signals if necessary. Avoid vias and stubs with noisy/sensitive signals.
Ideally, provide one ground wire per signal in a connector. Terminate connector signals, because they like to spew EMI. Ferrite beads around the wire can help with connector noise, too. Keep signals from going underneath connectors.
The ground plane allows you to create microstrip traces, which have a well-defined impedance. You can also use termination resistors if your trace is long. I think the general rule of thumb is for every nS of rise time, you can go 2.5" without a termination resistor.
Use IBIS simulations to determine whether you need termination resistors. Modern FPGAs have nice tricks for this sort of thing; they can control their output driver strength, sometimes even with a "Digitally Controlled Impedance" (Xilinx term for the technology). IBIS simulations help here, too, when figuring out the appropriate drive strength.
Check out Dr. Howard Johnson's humongous list of High Speed Digital Design newsletters. Truly awesome. http://www.sigcon.com/pubsAlpha.htm