I'd like to design a PCB for an analog loop controller.. something with an A/D, D/A, and processor on board. (Either DSP or FPGA, I haven't decided.) Since this should modulate analog signals at 10 kHz, it needs to be quite a fast processor.

From what I understand, designing a board for processors running above 150 MHz or so can be very challenging due to RF problems. What are some advice you can provide in designing such a board? What problems due to layout can occur? Are there any good online resources that have knowledge bases for this?


  • 2
    \$\begingroup\$ Are you sure you need that much processing speed? 10 kHz doesn't sound too fast. Perhaps something like an ARM7 or dsPic will be sufficient. \$\endgroup\$ Nov 27, 2009 at 22:57
  • \$\begingroup\$ depends on the control loop's details and requirements: phase margin is impacted by the latency from input to output of the control algorithm. If the signal processing is complicated, that will take more cycles than if it's simple. If the phase margin requirements are stringent, you will have less time available. Better to design a board with a bit of a surplus of CPU power, than to design a board with a bit of a deficit, as you can always make things slower. \$\endgroup\$
    – Jason S
    Nov 28, 2009 at 4:59
  • \$\begingroup\$ thanks, it's true, timing is critical in this application. i didn't want to get into it, but actually the output should be computed within the time of one sample, so latency is key. \$\endgroup\$
    – Steve
    Nov 30, 2009 at 21:05
  • \$\begingroup\$ Steve: It is quite difficult not to compute the output in time of one sample since this means you are not real-time anymore and won't be able to control anything. \$\endgroup\$
    – jpc
    May 8, 2010 at 21:55

6 Answers 6


If you're interested in high speed digital, get a copy of High Speed Digital Design.

Key points:

  • The main determining factor of you circuit is the rise time of the logic. Even if you operate at a slow clock rate, fast edges can create problems.
  • The maximum rise time of your system then gives you the critical length of your circuit. Essentially if the propagation delay of your signal over the length of the circuit is longer than the rise time of the signal, you need to worry about the high frequency aspect of the design.
  • If it turns out the critical length is shorter than the circuit layout, then you need to use controlled impedance layout. This includes:
    • Track geometry (track width and hight above a ground plane) to give the circuit a defined characteristic impedance.
    • Terminating the drivers and/or recievers with the line's characteristic impedance.
  • \$\begingroup\$ I have gotten this book, it is absolutely fantastic. I am only on chapter 3, but the first three chapters have both taught me new material and made me think of material I know in different ways. \$\endgroup\$
    – Kortuk
    May 8, 2010 at 7:55
  • \$\begingroup\$ Almost a quarter of a century later, a handbook of black magic is still the definitive piece of literature on the subject. \$\endgroup\$
    – Cort Ammon
    Jul 15, 2017 at 0:36

Use a full ground and power plane. Bypass caps are limited by inductance, which is mostly determined by package size, traces, and vias. So pick the smallest package size that you can work with, then go for the largest capacitance that doesn't break your budget. If you need more bypassing, go up a package size or two and get the biggest capacitance in that package. When connecting the cap to the ground/power planes, use two vias on either side of each pad; vias + cap will look kinda like an H.

Splitting the planes can help isolate the analog and digital sections. Never cross a split plane with a signal trace!!! Keep signals away from the edge of the board. Keep signals at least 2x trace width apart to prevent crosstalk (simulations are helpful here). Keep signals 5x trace width away from highly noisy signals (i.e. clocks) or extremely sensitive signals (i.e. analog inputs). Use grounded guard traces around noisy/sensitive signals if necessary. Avoid vias and stubs with noisy/sensitive signals.

Ideally, provide one ground wire per signal in a connector. Terminate connector signals, because they like to spew EMI. Ferrite beads around the wire can help with connector noise, too. Keep signals from going underneath connectors.

The ground plane allows you to create microstrip traces, which have a well-defined impedance. You can also use termination resistors if your trace is long. I think the general rule of thumb is for every nS of rise time, you can go 2.5" without a termination resistor.

Use IBIS simulations to determine whether you need termination resistors. Modern FPGAs have nice tricks for this sort of thing; they can control their output driver strength, sometimes even with a "Digitally Controlled Impedance" (Xilinx term for the technology). IBIS simulations help here, too, when figuring out the appropriate drive strength.

Check out Dr. Howard Johnson's humongous list of High Speed Digital Design newsletters. Truly awesome. http://www.sigcon.com/pubsAlpha.htm


I know very little about high-speed layout. But the thre common things I've heard are: Avoid right angles for signal traces (they cause reflections), have a ground plane over as much of your circuit as much as possible, and partition your board to have similar signal types (low-speed digital, high-speed digital, analog) into different areas, with "choke points" in your ground plane to minimize interference.

As for good online resources, I would imagine the datasheets & appnotes for the DSP or FPGA you're considering will have some good tips. I remember Xilinx having good stuff.

  • \$\begingroup\$ Avoiding right angles --- do you mean literally making rounded corners on traces? (Unless it can be a straight line I guess.) \$\endgroup\$
    – Steve
    Nov 27, 2009 at 22:29
  • \$\begingroup\$ I think he means that you can have angles just not at 90 degrees. I haven't seen any rounded corners, well, in a long time. But if you look at the motherboard in your PC youll also see all corners are much less than <90 degrees. If the line needs to go 90 then it will often be split into, well, maybe a few 30 deg angles \$\endgroup\$
    – cyphunk
    Nov 28, 2009 at 0:02
  • 4
    \$\begingroup\$ Two 45 deg angle corners is typical. But using transmission line tracks and proper termination is more important than corner style. If you don't have terminated transmission lines, then different corner styles won't make any difference. \$\endgroup\$ Nov 28, 2009 at 0:22
  • \$\begingroup\$ two 45degree angles is very common as in a trace they have excellent matching properties, I will find a guide later that explains what design considerations to take into account to do this properly. \$\endgroup\$
    – Kortuk
    Nov 28, 2009 at 14:20
  • 1
    \$\begingroup\$ Today I ran across some auto route software that does infact use curves. eremex.com/products/topor/competitiveadvantages/… \$\endgroup\$
    – cyphunk
    Dec 2, 2009 at 14:03

To address your application rather than the question you asked directly (the other answers have talked about this):

10 kHz DSP for a loop controller isn't too fast. (we use 5 or 10kHz control loops for motor controllers) With a decent device, my guess is you should be able to handle it with a clock frequency of 40-80MHz if you had to, and the neat thing about the newer series of DSPs and microcontrollers is that they use phase-locked loop (PLL) clock multipliers to boost the clock frequency internally, so that externally there don't actually need to be any really fast signals. TI's TMS320F28xx series of DSPs (see the 28044 and 28235) have a 5x PLL (half-steps from 0.5x to 5x), so you can get a 100MHz clock with a 20MHz crystal.

For the digital side, what you need to watch out for most, is making sure you provide a good solid pair of power and ground planes for your processor, and make sure you add bypass capacitors as close as possible to the processor's power supply pins. Also instead of just sprinkling a bunch of 0.1uF capacitors, use a variety of 0.1uF, 0.01uF, and 0.001uF capacitors. The 0.1uF capacitors provide more charge but their parasitic inductance comes into play at a lower frequency than what you'll see on a 0.01uF or 0.001uF capacitor. The latter two will not provide as much charge, but will work properly as bypass caps out to a higher frequency. We had a board design that was working but had a moderate amount of noise on the DSP's analog-to-digital converter. One of our engineers actually made some high frequency measurements with a scope probe with the "witch's hat probe tip off", directly with the probe terminal and ground ring, and modified the bypass capacitors until he saw the power supply voltage noise reduced sufficiently.

The analog to digital conversion is going to be the weakest spot in your system. You probably won't have to work too hard to get the digital system working ok. But unless you're careful, you'll get mediocre noise performance on your ADC. (I'm afraid I don't have much experience personally dealing with this; other engineers at our company handle the layout, so what I'm telling you is second-hand.) How to handle ground planes is something that is argued by two separate approaches: whether to use one huge ground plane for the whole system, vs. two separate ground planes, one analog + one digital, tied together at the ADC -- the former is fine for 8-10 bit systems, and I hear separating digital/analog areas of the circuit is more important when you get to higher bit counts (16bit or higher).

Don't skimp on # of board layers. Ground and power planes are your friends.

  • \$\begingroup\$ I think a dsPIC can easily work on a two layer board, it just requires a very careful layout. Your answer was clear and concise though. \$\endgroup\$
    – Kortuk
    May 10, 2010 at 4:34
  • \$\begingroup\$ I agree. 10kHz really isn't that fast. We have 10MIPS PIC18s which spend half their time running a 5kHz control loop, and the rest of the time doing other stuff. They only need a 10MHz clock, and hardly any special considerations for high speed design. \$\endgroup\$ Mar 28, 2012 at 19:42

Read up on ham radio or find an Extra Class operator to help. We deal with these problems all the time at much higher frequencies. We also use DSP processing in nearly all of our equipment. Try the AARL education stuff online, or QRZ. The problems aren't that hard to correct for but there are a lot of possible problem areas to watch out for.
73, KF7BYU


As already mentioned you can use a fast processor with a PLL and still have only your 10kHz signals + a 12MHz quartz oscillator (close to the CPU) on your board. To lay this out will not be a problem.

Many people (me included) did 48kHz stereo audio output on an ARM7TDMI (streaming from an SPI connected SD card in my case). I even saw mp3 decoding in software on a 50MHz ARM7 running from RAM (there may be wait-states when working from Flash).

Maybe buy an mbed LPC1768 board (100MHz, very fast ADC/DAC and PWMs on-chip, cheap: 50€) and make a prototype? Only if this is not sufficient start playing with other (more costly and difficult) stuff.


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