Recommendation for sine wave of 100kHz with 1ppm stable amplitude

Question

I need to design a 100 kHz sine wave with 1 ppm stable amplitude. I mean the noise of the amplitude should be lower than 1 ppm RMS and also the thermal stability should be < 1 pmm/K. I was thinking of a Colpitts circuit with a crystal oscillator.

Answer 1

Setting aside the fact that your specifications are not very complete, here's how I would go about quickly getting something stable enough to start experimenting with.

There's a little-known circuit for shaping single tones from a higher frequency logic clock, that generates exact amplitudes, rather than the approximate ones that a general DDS would.

The following diagram shows its implementation with a 6 stage shift register performing a divide by 12, though by using suitable resistor values, you can use any larger number of stages to get a higher division ratio.

^{simulate this circuit – Schematic created using CircuitLab}

The resistors are simply the inverse (that is, have conductance) of the sines of angles 30 to 180 in 30 degree steps. I've shown R6 for completeness, even though it computes to zero conductance, or open circuit. If for some reason you wanted to shift the phase of the sinewave (to make 3 phases, or sine/cosine pairs) then it would have a finite value.

The output can be used as is, as a rail2rail voltage output of a few kΩs output resistance, or be driven into a small value resistor, like 50 Ω to drive a coax, or into a virtual ground amplifier.

Starting from here, you have an amplitude that's nearly as stable as your Vdd supply to the shift register. With the right technology shift register (I'd use 74AC, for speed and low output resistance), it won't add much noise to the supply. You would use a crystal-derived master clock. It's cheap enough, and the less noise you invite in from other sources, the better.

With many outputs in parallel, the output resistance is low, their noise is averaged, and individual resistors are much higher than the shift register output resistances. You can scale all the resistor values with a constant term, but these values seem reasonable. You need to keep them dominating the IC output resistances, which can be voltage and temperature dependent. There is no scaling that allows all the resistances for 30 degrees to be single values from the E24 series, so if you are using those, at least one has to be made from several resistors (11k + 560). I have not checked for whether all three are available as single resistors in the finer families (E48/96/192)

The design of this type of dividing clock to sine converter means that it has very low harmonics up to the 11th (for /12 division), so your low pass filter can be very low Q. When the resistors are exactly sine conductances, the harmonics are zero, but tolerances and allowances for shift register resistance means they will just be low, you could expect -40dB or better for 1% resistors.

One area of long term amplitude instability would be a shift of the corner frequency of your low pass filter with respect to the signal. A low order filter can be more stable than a high order one in this respect. If you wanted to increase the signal to corner frequency ratio, then divide by more than 12 (must be even), and choose resistors accordingly.

Your 1ppm aspiration is challenging, your test gear and test methods will be as difficult as your source. I would suggest you throw the above together, and experiment to see what you've got, and what you can measure, before embarking on further refinement, especially refinement of your specifications. I have found that I always learn something I didn't expect when doing a quick initial real experiment. One refinement that may be worth testing is to use CMOS switches instead of gate outputs to drive the resistors - they may be better, or worse, for noise and stability.