# Question on Turn-off Snubber Operation

I'm struggling to understand how this snubber circuit reduces power loss during the off time for this buck converter. Anybody able to explain it's operation / what is happening for each component during the off time and on time? I'm fine with how the buck converter operates.

• adamjohn1 - Hi, Where did that diagram come from? To comply with the site rule on referencing, details of each original source of copied / adapted material must be provided by you, next to that material. If the original source is online (webpage, PDF, video etc.) please edit the question & add its name & link (URL) (e.g. "Datasheet XYZ" & URL). If the original source was a book or other offline material, please edit the question & add a full citation e.g. title, author(s), page, edition etc. (see the linked rule for details). See the tour & help center for rules. TY Commented Apr 18 at 14:25
• I’d say due to the charge across C, this causes D1 to conduct slightly earlier than D2 helping to mitigate the loss. It also smooths the snap-on of D2 that may cause ringing in the inductor. Commented Apr 18 at 14:36

The idea behind this snubber is to reduce the power dissipated in the transistor during the turn-off event, when the transistor opens. When the switch turns off, the current is not instantly cut as it needs to divert to the free-wheel diode but the voltage across the collector and emitter (or drain-source with a MOSFET), will quickly rise, depending on the amount of capacitance across the transistor. Having a strong current together with the instantaneous rise of the voltage leads to a high peak power in the semiconductor. Depending on the level of this peak, you may exceed the safe operating area (SOA) specified by the semi manufacturer in the data-sheet.

I have assembled a quick circuit where you see a low-side switch interrupting an inductive current, later free-wheeling in diode $$\D_1\$$. When the switch turns off, the voltage across the switch will rise at a slope given by $$\S=\frac{I_p}{C_1}\$$ in which $$\I_p\$$ represents the current at the turn-off event and $$\C_1\$$, the capacitance lumped at the drain node. It is a nonlinear element but represented as a simple capacitance here for simplicity. The (idealized) waveforms are shown below:

You can clearly see the overlap of the current and voltage during the opening and the peak power it brings. This turn-off loss is dissipated in heat and the average value scales with the switching frequency. The ideal situation would be that the switch is still turned off quickly, but the voltage across its terminals does not rise that fast, giving time to the current to fall down to zero. According to the slope formula I gave, we can increase the capacitance across the transistor:

The capacitance delays the rise of the drain-source voltage and reduces the overlap portion, bringing the peak power down to 350 W.

That is cool but now, this capacitor is fully charged at the input voltage and, when you turn the switch back on again, you incur a turn-on loss now contributed by the capacitor intended to cool down the transistor. Depending on the converter, this capacitor can sometimes be discharged using resonant techniques but in hard-switching structures, you need to take care of its charge.

To limit the power dissipated in the switch at turn on, you add a series resistance which is going to divert a part of the dissipation budget from the transistor to the resistor, offering a safer switching environment for the semiconductor. Unfortunately, this resistance introduces a time constant meaning that if too big, you do not fully discharge the capacitor during the on-time but, at the same time, you defeat the purpose of the added capacitance to slow down the $$\V_{DS}\$$ at turn off by adding an offset. You fight this collateral offset by adding a diode in parallel with the resistance (it shorts it at turn off) but you are forced to limit the resistance value to ensure a full discharge at turn on.

Snubbing is almost a specialty in itself in power electronics and you will find many guidelines and application notes showing how to design these snubbers.

I don’t think this improves the power losses since all energy in cap is burned on resistor (parallel to D1) at the beginning of Ton.

But what this circuit improves is an EMI since the voltage derivation on cathode of D2 is reduced.

D2 has enough time to start conduct because the cap slows down the D2 cathode voltage fall.

Also it helps to reduce inductor leakage ringing.

• They can, in fact, improve efficiency; just not usually by much, and under limited load conditions. See fscdn.rohm.com/en/products/databook/applinote/discrete/sic/… for example. (I recall reading a more dramatic claim in an older paper -- perhaps it was Unitrode, or ST something or other, but I can't seem to find it offhand -- that claimed up to a 15% reduction in switching loss with optimal snubber values. The impact is probably much less with modern devices -- SiC and SJ MOSFETs, over planar, or BJTs even.) Commented Apr 19 at 11:27