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I am designing an anti-aliasing LPF for a 16-channel ADC on a custom STM32F415-based board. This design will ultimately be put on a car and used as a DAQ.

I am planning on running the ADC with a 30 MHz clock in dual interleave mode, which results in a maximum sample rate of 3.75 Msps. From my understanding, this results in a Nyquist frequency and usable sample rate of 1.875 MHz maximum.

The goal is to sample the ADC at 1 MHz using DMA, as the system will be processing some other signals as well.

The signal must be stepped down from the 5 V sensor signal as the STM32F4 runs at 3.3 V. The current design I have for that is a resistor-based voltage divider using 1 kΩ and 2 kΩ resistors, respectively. I believe this should be done before passing the signal through the LPF to reduce the noise that gets through to the ADC.

If I understand correctly, these would be the theoretical ideal values for the filter:

  • Passband up to 1 MHz
  • Transition band from 1 MHz to 3.75 MHz
  • Stopband at 3.75 MHz

From playing around with some filter design tools, to fully implement this, I would need a high-order filter. The goal is to keep costs reasonable, so I would prefer not to have +$100 in op-amps.

The current design I have created is a second-order Bessel filter that I think will do a good job balancing circuit complexity and performance. Below is an image of the circuit from TI's filter design tool (Without the voltage divider).

2nd-Order Bessel Filter

I think this would be a good design, but I am relatively new to this so I would like some input. Is it worth implementing a filter like this? Should I keep it simpler with a passive filter? Should I commit to a 3rd- or 4th-order filter and deal with it on the board design side? Is there a better way to step the voltage down?

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    \$\begingroup\$ That's an inverting op-amp circuit. If sensor outputs 1V, the opamp outputs about -1V to MCU. And it needs negative supply to work. What voltages you have available, and what attenuation you need at sampling rate? Also, if you intend to sample at 1 MHz, your filter needs to have good enough attenuation at 500 kHz, setting the cutoff point much below 500 kHz. \$\endgroup\$
    – Justme
    Commented Apr 18 at 21:07
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    \$\begingroup\$ Ditto the above and, what sort of signals might you be having to get rid of to prevent aliasing? \$\endgroup\$
    – Andy aka
    Commented Apr 18 at 21:50
  • \$\begingroup\$ What are the sensors? Do you really need that much bandwidth? What accuracy do you need to read them with? (Includes temporal resolution, e.g. maybe you don't need to know it very accurately from sample to sample, but you do need it accurate long-term.) This determines the cutoff and steepness of the AA filter, so are critical to the question. \$\endgroup\$ Commented Apr 18 at 23:49
  • \$\begingroup\$ @Justme, I designed this late last night and missed that it was inverting...oops. I will have 5V and 3.3V easily available. I guess I am a bit confused about the relationship between sample frequency and cutoff frequency. From what I understood, the cutoff frequency was supposed to be at the frequency of the ADC, not at the Nyquist frequency. \$\endgroup\$
    – ABashara
    Commented Apr 19 at 0:27
  • \$\begingroup\$ @TimWilliams The sensors are a combination of a few different things: The suspension pots are the most demanding bandwidth-wise, thermocouples for brake temps, some accelerometer data, and pressure sensors. They need to be fairly accurate in order to be able to use logged data to analyze vehicle performance. \$\endgroup\$
    – ABashara
    Commented Apr 19 at 0:54

1 Answer 1

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Defining the requirements for an anti-aliasing low-pass filter can be a little tricky and depends heavily on your use case.

What's the problem we are trying to solve?

Aliasing is the effect where signals that are sampled are "folded" across the Nyquist frequency, appearing at lower frequencies. We generally treat these as noise. If we remove these signals before they are sampled this noise disappears.

TI diagram showing frequency folding (Diagram from this TI app note)

How much noise rejection do we need?

This depends on two factors:

  • How sensitive your ADC is.
  • How much noise there is

How sensitive is your ADC?

The first factor is easy to figure out; for most applications, you can just look at your ADC's SNR (or, depending on your use case, SINAD, THD, SFDR, etc) in dB and target the noise to be lower than that value for it to not degrade your ADC's performance.

It looks like the STM32F415 datasheet does not have dynamic specs like SNR, so we can bound the problem with the SNR from its ENOB. ENOB (Effective Number of Bits) is a measure of the lowest noise an n-bit ADC can have based on the noise inherent in quantization. (You can learn about the pedantic detail here, disclaimer I wrote the content)

SINAD for an ADC with a n-bit ENOB is generally calculated as

$$1.78dB + 6.02dB \cdot N$$

So, a 12-bit ADC has a maximum theoretical SINAD of 74 dB (more about SINAD vs ENOB here).

How much noise do you have?

How much noise is tricky, for many applications. The first thing to consider is do you expect significant high-frequency (above Nyquist) noise while trying to acquire your normal signals.

Or, put another way, do you expect your signal, when viewed with an oscilloscope, to be swamped by high-frequency noise?

If not, you may only want to slap in a single pole filter with a cutoff at your highest frequency of interest; this is generally good enough for many applications.

If you do expect to see significant interference or a completely unknown signal (like for an oscilloscope frontend) you can limit the problem to the highest amplitude signal possible, a square wave from rail to rail on your input (generally clamped).

A square wave's fundamental frequency component is actually ~27% (2.1dB) larger than the amplitude of the square wave.

So if your input range is clamped to the input range of your ADC, then you would need SNR + 2.1dB or rejection. In this case 76dB.

How Sharp does your filter need to be?

The filter needs to have a response at Nyquist at or below the filtering value we worked out above to filter this noise out.

We can calculate the number of poles with the equation:

$$ N = \frac{\text{Rejection Required (dB)}}{20} \Big/ \log_{10}\left(\frac{\text{Nyquist}}{\text{Cutoff Freq}}\right) $$

So the highest the filter cutoff can be for a single pole filter to get 76dB of rejection is 0.016% of the Nyquist frequency, 1.3% for 2 poles, 17% for 5 poles, etc.

How can we do better?

If we take advantage of the fact that digital filtering lets us achieve much higher cutoffs (effectively a brick wall), we can actually relax the filter to allow leakage all the way back to our passband, letting us trade digital complexity for analog complexity.

enter image description here

This means we only need:

$$ N = \frac{\text{Rejection Required (dB)}}{20} \Big/ \log_{10}\left(\frac{2 \text{ Nyquist}-\text{Cutoff Freq}}{\text{Cutoff Freq}}\right) $$

Reducing our 76dB filter requirements to 0.03% at 1 pole, 2.5% at 2 pole, 30% at 5 pole, etc.

Applying it to your problem

A 2-pole passive RC filter is almost as good (for many applications) as a 2-pole active filter. If you really expected to see extreme noise without digital filtering, you could set your cutoff at 24kHz, with a 2-pole filter to get -76dB at Nyquist (this would be extreme overkill, I suspect).

You mentioned in your application you are sensing suspension pots. Generally, vehicle suspension response is in the single-digit to the low double-digit range, so sampling at one or two ksps with a 15 or 20Hz single pole filter should be just fine.

Additional Notes

Delta-sigma ADCs sample at a very high frequency, generally with a 1-bit ADC many times the Output Data Rate (ODR); loosely delta-sigma ADCs work by filtering a high bandwidth single-bit ADC to produce a low bandwidth many-bit outputs.

This means you only need to provide anti-aliasing filtering to meet the Nyquist frequency of the sample rate, greatly relaxing the filtering requirements.

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