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I have been working on an optional differential op amp using BJTs and cant seem to achieve the above goal. I have a current mirror in place and have been trying to configure the circuit below to remain in active mode. The problem is when gets to the second stage amplifier the current mirror I think is placing it in saturation. The circuit I designed after is similar to what I have covered in class. If anyone has any suggestion on how I can get the second amplifier out of saturation and remove its DC component I could take it from there.

schematic

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    \$\begingroup\$ Please clarify your specific problem or provide additional details to highlight exactly what you need. As it's currently written, it's hard to tell exactly what you're asking. \$\endgroup\$
    – Community Bot
    Apr 21 at 21:51
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    \$\begingroup\$ Hi Elizabeth! This is nice, you already have a suspicion what goes wrong. How would you use your simulation to verify whether the transistors in question are already in saturation? And: you want 500 V/V gain, right? So, given your 50 mV input, what would be the output amplitude, when your circuit works correctly? How does that relate to your supply voltage? \$\endgroup\$ Apr 21 at 22:51
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    \$\begingroup\$ Hi, yes, I agree with @MarcusMüller. Suggest reducing the signal to just 0.1mV. Does the output respond as you expect? If the gain is correct, then the output amplitude should be 50mV. If that is all good, then start to increase the input signal and see which stage is saturating. \$\endgroup\$ Apr 21 at 23:33
  • \$\begingroup\$ You should at least label node quiescent voltage \$\endgroup\$
    – Willis Lin
    Apr 22 at 1:21
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    \$\begingroup\$ R1 seems to be wrong. Shouldn't that be 4.7k? This first stage diff-amp will have very different collector potentials, causing everything else coming after to saturate. \$\endgroup\$ Apr 22 at 6:11

3 Answers 3

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That first stage differential amplifier's output amplitude won't be large (because the second stage will have gain as well as the first).
Since 1st stage collectors can lie in the region between near-zero volts up to +10V, you can DC-bias it so its collectors idle near the bottom of this range. This will leave voltage headroom for the 2nd stage collectors to swing over a larger range.
Since your current sources feed the same current to each differential stage, you're free to choose collector resistors for first stage (R1, R2) different from collector resistors for second stage (R3, R4). To achieve DC bias headroom as mentioned above, first stage collector resistors should be chosen larger than second stage collector resistors.
You'll still need to add a DC offset to 2nd-stage collector outputs, however - if you want to simulate an op amp.


Do you intend to breadboard this design?
I've done this exercise, and its not easy, because 2N2222 are never similar-enough to each other. This means that DC bias is really hard to get balanced so that output voltage doesn't hit a power-supply rail. I ended up balancing the DC bias point by heating one of the differential amplifier input transistors with a finger.

This problem is less-severe if transistors are integrated into a chip - they all operate near the same chip temperature, and their characteristics all nearly match - aiding balance.


I'll point out a modification to this basic circuit that appears in many, many chips. For example, this topology is used in emitter-coupled logic digital chips. Also used to amplify analog signals in FM radio limiter stages. By adding a unity-gain buffer transistor between stages, every stage is identical, and stages can be cascaded many times...

schematic

simulate this circuit – Schematic created using CircuitLab

In this case, two cascaded, identical stages are shown. out- and out+ don't need to be offset - this amplifier can apply negative feedback back to the input stage just like an opamp...feedback seeks a stable, symmetrical DC bias point.
Adding the buffer stage doesn't allow a large output swing before it goes non-linear, so it is only a linear amplifier over a small voltage range.

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Here are some suggestions to improve this design:

  1. Remove R6, or replace with much lower value R, say, 100r. It is not doing much except reducing the power dissipation in Q8. At ~1mA of bias current, Q8 will only dissipate about 10mW with no-signal applied, which is well within its rating. A large value for R6 will only limit the maximum negative voltage swing.
  2. The voltage at the collectors of the first diff pair Q1, Q2 will set the upper limit of the output voltage swing. So you may have to consider moving that bias voltage upwards towards the +10V rail, by various means (reducing R1 & R2, or reducing bias current of Q1 Q2, or both).
  3. The second diff pair stage needs to be "flipped" to a PNP pair and fed from a current source connected to the positive rail, and collector resistors connected to the negative rail. Think about it: with the circuit in the OP, how much voltage swing is available at the base of Q7? Can this voltage even reach 0V? Hint: Q6 collector voltage cannot go below its emitter voltage. If this is done then, accordingly, Q8 becomes the voltage follower of the output stage, and Q7 becomes the constant current source.
  4. R8 and R7 may need to change to lower values. The voltage gain of this second stage is very low. Also consider putting emitter resistors at the first diff pair, to (a) better control its gain, and (b) limit effect of transistor mis-match in real-world components.
  5. Put an R in series with each emitter of the current sources (Q3, Q4, Q10, Q9, Q8). Select this R to drop about 50mV to 100mV, this stabilises the current sinks (or sources) against variations in Vbe of the transistors. This is not important for simulations because each transistor is identical, however, in the real world, real transistors vary from unit to unit.
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Should R1 be 4.7kΩ? It's currently 4.7Ω, causing collector potentials to be very different, which would easily saturate the second stage.

Also, you are currently relying on transistor transimpedance to set the gain, which will probably be well above the 500 you desire. Open loop gain is probably sufficient, however, that negative feedback will linearise the response, and enable you to set gain very precisely. Here I set feedback to 0.2% using a resistor potential divider (R1 and R2), for a gain close to 500:

schematic

simulate this circuit – Schematic created using CircuitLab

I'm not sure that feedback here is negative, because I haven't tracked inversions very thoroughly. If it doesn't work as I have shown, try swapping the signals at the bases of Q1 and Q2, which would change feedback polarity.

The goal is to obtain a closed loop similar in structure to this, with which I am sure you are familiar:

schematic

simulate this circuit

Negative feedback will also cause the whole amplifier to bias itself, so that a zero-volt input from V1 should result in near-zero-volt output. I say "near", because there will be significant input offset voltage due to transistor mismatches, and that offset will also be amplified by a factor of 500.

I would recommend starting with significantly lower closed-loop gain (say about 10, with R1≈5kΩ). That way you don't confuse saturation due to input offset with saturation due to a fault in the design or construction.

This will be an opportunity for you to explore the effects of input offset voltage and input bias currents, which will both be significant here, if this circuit were to be physically constructed using discrete transistors. In a simulation, though, the transistors will be perfectly matched, and offsets will not be so apparent.

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