I need some help with a circuit I can’t find much information online. Basic function should be a LDO which can source and sink current. To make it a bit more challenging there are some further requirements:

  • Single supply only
  • Should also work when near to the VIN rails (see 3 below)
  • To prevent some cross conduction in the output stage I implemented a common collector amplifier I am not 100 % familiar with. (maybe not even 50%)

Here is the circuit I came up with; enter image description here


  1. Looking at the common collector part of the circuit: Are the resistors around it selected correctly? I have the feeling that base current is pretty high
  2. What can I do to make the common collector part of the circuit more unacceptable to VIN changes? R1 and R11 are now selected to fit to gate voltage threshold for given VIN voltage. But changing the VIN also requires changing these two emitter resistors.

Some additional explanation why I did choose this topology:

  1. Idea gave me an obsolete Maxim patent: https://patents.google.com/patent/US6437638B1/en

  2. I just have single supply and don’t want to generate an additional voltage to use a NMOS as high side driver like in the patent 1

  3. The output voltage should be adjustable near to the VIN rails, why it made sense to use a PMOS as high side driver and a NMOS as low side driver – which also forbids using a traditional AB linear output stage

  4. EDIT 1:Additional information for Simons comment below showing the switching behavior from on mos to the other: enter image description here

  5. EDIT 2: Showing gate voltage seperation with voltage source sweep. enter image description here

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    \$\begingroup\$ With Q3 and Q4 as emitter followers following the the same potential, the gates of M1 and M2 will never be more than 1.4V different. This will ensure that M1 and M2 will be switched on simultaneously, most of the time, causing shoot-through. You'll need some mechanism in place to ensure that this cannot happen. Something that will disable one of the MOSFETs when the other is "active". This is not an issue in a traditional common-drain push-pull output stage, but in this common source configuration it's a problem, unless \$V_{IN}\$ is smaller than the sum of the two FETs' \$V_{GS(TH)}\$. \$\endgroup\$ Commented Apr 23 at 14:26
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    \$\begingroup\$ You should replace OPAout with a voltage source, and sweep that from 0 to 5V to see the interval in which both FETs are on. That state is not apparent in your simulation, because the op-amp output slews too quickly through that interval. \$\endgroup\$ Commented Apr 23 at 15:08
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    \$\begingroup\$ Also, R2 and R12 keep Q3 and Q4 permanently saturated. I'm not sure what the purpose of those two resistances is, but I think they cause Q3 and Q4 to behave no better than a couple of diodes. I think you'll need a better way to separate the gate potentials. \$\endgroup\$ Commented Apr 23 at 15:10
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    \$\begingroup\$ Yes, remove R2 and R12. The diodes in your last linked schematic are to bias the push-pull pair of Q10 and Q11, not the MOSFETs. It seems that when Q10 and Q11 current limits are reached (as sensed by R16 and its unlabelled high-side counterpart), the MOSFETs become biased on, taking over. \$\endgroup\$ Commented Apr 23 at 15:39
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    \$\begingroup\$ The two MOSFETs in your design both have minimum \$V_{GS(TH)}\$ of 1V. The simulated models are likely above that, and may not exhibit shoot-through, but you should design for worst-case, meaning that you need at least 3V separation of gate potentials. Remove the load V4, and in your MOSFET models set thresholds to 1V. Then plot drain current as you sweep, to see shoot-through. \$\endgroup\$ Commented Apr 23 at 15:49


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