I have a three-state circuit which flips the polarity of a small resistive load using two push buttons.

The input is some battery voltage, between 10V and 25V DC. The output is two pins: A and B. The current limiter is about 10mA.

System Schematic


simulate this circuit – Schematic created using CircuitLab

Default state is VAB = 0V. When SW1 is closed, VAB = VBAT. When SW2 is closed, VAB = -VBAT. When both SW1 and SW2 are closed, the output is current-limited to 7 mA and VAB = 0V.

Everything works fine on LTSpice. But the real deal does not work.

LTSpice Model


The circuit was implemented on a PCB. I built a batch of four boards and reflowed them. No malformed/shorted traces on the PCB as verified with Ohmmeter. Very simple circuit overall.

Test Conditions

Let VBAT = 25V, without any load attached to A,B:

When SW1 is Closed, VA->GND = 13.5V, VB->GND = 0.01V, I=7mA ->When current limiting diode is bypassed with +25V to +BATT, Q2 shorts to ground and smokes. Nothing happens to Q1.

When SW2 is Closed, VA->GND = 0.01V, VB->GND = 24.6V, I=2mA ->When current limiting diode is bypassed with +25V to +BATT, Q1 still conducts about 2mA, nothing happens to Q2.

When SW1 and SW2 are open, RA->GND = 0.8Meg, RB->GND = 0.8Meg. VA->GND = 0.3V, VB->GND = 0.3V.


Seems to me like the MOSFETs are conducting electricity, even when the Gate voltage is clearly below Vgsth. They're conducting between 2 - 7 mA of current as measured by the power supply. R1 and R2 only contribute about 1.2 mA of draw. I have tested this circuit with R1 and R2 removed as well, with the same effect.

This same behavior has happened on multiple boards - not a single one works. I have switched out MOSFETs at least four times, even replacing them with MOSFETs from a different manufacturer, and the same thing keeps happening. The G,S and D are in the correct orientation.

The MOSFET should be able to handle everything. At no point do we ever exceed Vgs of +-30V. The resistors help discharge any residual capacitance in the system, so that we get lower Current spikes when the switches are engaged. According to the LTSpice model, we never exceed 1mA through either MOSFET when a switching event occurs. And the switching event is on the order of tens of uS.
DMN67D8LW Safe Operation Limits DMN67D8LW Datasheet Page 4 Figure 12, https://www.diodes.com/assets/Datasheets/DMN67D8LW.pdf

Does somebody else see something I am missing here? Or do I just have a bad batch of MOSFETs?

[EDIT 4-25-2024]

Wow, Electronics Stack Exchange is pretty helpful! Didn't think there would be so many responses.

By the way, thank you @Vicatcu for your CircuitLab Simulation. In the DC steady state simulation, everything worked great. Now the question remains, why isn't the real deal working?

Nevertheless, there's a lot of data here to go over. Basically the problems are more noticeable when VBAT goes above 13V.

All voltages are measured relative to system ground. @Voltage Spike, We can be assured that VA = Vgs Q1, and VB = Vgs Q2 due to the electrical connection through the PCB. So long as the solder joints are good, and the amperage is low, the ground is common for all the components. Just to make sure, I did measure the gate pins directly, and they are equal to the corresponding A and B pads. And thanks for the pinout reminder - this I have gone over many times just to make sure.

I have built fresh boards from the ground up six times with brand new components, and I keep getting the same results. I have done both Reflow and Hand Soldering in different instances. I have used a proper Flux, an ESD Mat, insulating gloves, the whole nine yards. I track Reflow temperatures and profiles in my oven with three thermocouples, two on plate and one in air, plus I use distributed Thermal Stickers to make sure the temperature never exceeds 260 deg C. I recognize Mosfets are particularly sensitive to temperature, ESD, voltage and even amperage. @Jens, I added 33 kOhm chip resistors to the PCB directly across the MOSFET leads. I double checked joint quality with an inspection magnifying lens.

Take a look at this table of measurements.

The voltages and amperages are measured with a Fluke 179. Everything was soldered down with quality connections, and the power supply clips are firmly clamped onto the feed wires. The output clips are firmly clamped to the multimeter. The results are fairly consistent among each of the boards.

Here is the test circuit wiring diagram:


Physical Wiring Diagram

Table of measurements

So why is it that Q2 conducts so much more than Q1? Why is this happening on every single board I checked? Why 13V?

front pcb back pcb

Captured on Digilent Analog Discovery 3. Signal 1 is VA, Signal 2 is VB.

Switch 1 closing, rising capture enter image description here Switch 1 opening, falling capture enter image description here Switch 2 closing, rising capture rising capture, sw2 Switch 2 opening, falling capture enter image description here

The oscilloscope maxes out at about 100 MHz, and the signal appears to be clean as a whistle. Maybe the gate is oscillating at super high frequency? Which may be keeping the gate partially open? I can't imagine how the circuit could maintain such a condition for very long. But we will add the RC filter to the gates next.


Solution was to add an RC Filter as suggested below. WOW!

  • \$\begingroup\$ MOSFETs upside down? \$\endgroup\$
    – winny
    Commented Apr 24 at 17:31
  • \$\begingroup\$ If I go from the schematic, then there is no pulldown on the FET gates. Since the gate behaves like a capacitor, it will maintain its charge and continue to be on even when the switch is no longer pressed \$\endgroup\$
    – Tyassin
    Commented Apr 24 at 17:53
  • 1
    \$\begingroup\$ @Tyassin There are pull-downs, it's just that the schematic is drawn in an obtuse manner. Node A is connected to one gate, one drain and one pull-down resistor, as is node B. \$\endgroup\$ Commented Apr 24 at 17:58
  • 1
    \$\begingroup\$ I had a similar issue some months ago with a series of PCBs. The copper was not fully removed by the acid. There was an invisible copper cloud of more than one square inch left and between some tracks I could measure 10-100 kohm. This was more or less the same on all 20 boards. Can you check this on a blank PCB? I need an explanation for 2.31 mA at 24.7 V if there is only 33 kohm nominal load. \$\endgroup\$
    – Jens
    Commented Apr 26 at 2:00
  • 1
    \$\begingroup\$ It may be prudent to mention that D3 is not actually a diode, it is actually a constant current source. Datasheet here: onsemi.com/pdf/datasheet/nsi50010y-d.pdf \$\endgroup\$ Commented Apr 27 at 21:31

3 Answers 3


Insert an R-C network before each MOSFET gate, refer image below (I've only drawn one, you will need to repeat this on both MOSFETs).

enter image description here

  • 1
    \$\begingroup\$ Yes, I thought the same. There might be an oscillation >> 100 MHz, but I'm not convinced. We can exclude that with this test. \$\endgroup\$
    – Jens
    Commented Apr 26 at 2:07
  • \$\begingroup\$ IT WORKS! You did it! You guys are genius... How did you know this? Why can't my oscilloscope pick up on any oscillations? \$\endgroup\$
    – biobuilder
    Commented Apr 26 at 4:39
  • 2
    \$\begingroup\$ @biobuilder Glad to hear it. The reason the scope is not showing this is because connecting the probe may be actually be stopping the oscillations (the probe adds some parasitic capacitance). This is the electronic equivalent of the observer's paradox in quantum physics: making the observation changes the outcome. :-) \$\endgroup\$ Commented Apr 26 at 5:01
  • \$\begingroup\$ If this solved your problem then please upvote my answer, and select it as "Accepted answer". Thank you! \$\endgroup\$ Commented Apr 26 at 5:03
  • \$\begingroup\$ You're right, even a small addition will affect the result. It's hard to see how a DC system could be so... AC. And yet it was. Well, they don't pay you the big bucks for nothing. \$\endgroup\$
    – biobuilder
    Commented Apr 26 at 5:09

A few things

  1. Put a meter between the Gate and Source and measure Vgs. Make sure Vgs is postive and check it against the datasheet. In the LTspice simulation, you have ground, your ground may not be ground on your board with wires and other things in the circuit. It may be preventing you from reaching Vgs

  2. Test the mosfet with a bench supply (or two one for the gate, use proper grounding and ESD) with a series resistor on the source and verify that the mosfet is turing on. The current of the fet should be off when Vgs is 0. You could also try shorting the gate to ground, you should observe no current. Slowly ramp up Vgs and watch the current go up on the supply. If you can't see the fet switch on while it's on the bench then you must have a bad fet.

  3. Make sure the pinout is correct. I've ran into at least one instance where there was a fet with two different pin orientations and also layout inconsistencies with the schematic. For most people and you this probably doesn't need to be said, but it is an issue.

  • \$\begingroup\$ Did you check Vgs when Vbat is 13V, what is it? \$\endgroup\$
    – Voltage Spike
    Commented Apr 25 at 21:51
  • \$\begingroup\$ What you have simulated is not even close to the real world, you should make your model like the real world. \$\endgroup\$
    – Voltage Spike
    Commented Apr 25 at 21:52
  • \$\begingroup\$ Also draw a diagram of your picture, just by looking at the picture it's hard to know where your leads are going . \$\endgroup\$
    – Voltage Spike
    Commented Apr 25 at 21:54
  • \$\begingroup\$ yep, somehow I'm not running the sims right. I simulated the circuitry on LTSpice to see if there were any transient current spikes, and I'm pretty sure they're well under tolerable limits. So I think there's something else going on here that I'm just not seeing. Also, I added a physical description of the wiring, plus another CircuitLab circuit showing how the voltages were measured. All simulated versions work great. I don't see how I am exceeding Vgs. Nor are we ever exceeding Ids max, ever. Even when the switch closes fast, the total residual cap potential is kept low by the pulldown \$\endgroup\$
    – biobuilder
    Commented Apr 25 at 23:51
  • \$\begingroup\$ When Vin = 13V, Vgs is 12.83V for Q1 when SW1 is pressed, and Vgs is 12.23V for Q2 when SW2 is pressed. The current limiter D1 drops the voltage a little more when Q2 is active than Q1. The effect gets especially pronounced as Vin increases. It's almost like current is leaking through the Gate, or somehow the current is leaking through the body when Vgs = 0. \$\endgroup\$
    – biobuilder
    Commented Apr 25 at 23:58

Solution: Add an RC Filter on the MOSFET Gate.

As suggested by @Fabio Barone, and affirmed by @Jens, there must be some kind of high frequency noise, beyond 100MHz, which causes the gate to partially open while active. The Digilent Analog Discovery 3 didn't detect a thing. Blew my mind when I tried this solution. Please see the revised circuit, which actually does work in real life now:


simulate this circuit – Schematic created using CircuitLab

Thanks Electronics Stack Exchange Crew! I learned something today about high frequency noise on MOSFET gates. Sometimes, it's just better to filter the gate. I may not have ever had this happen before in a circuit, and I've built many circuits with MOSFETs in them. Never thought it would show up in something as simple and clean as this.

front side

back side


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