Skip to the last schematic for a working model, but read on for some semi-rigourous reasoning why your own design doesn't work.
The diode equation is:
$$ I = I_S \left(e^{\frac{V}{\eta V_T}} -1 \right) $$
With \$V\$ as the subject, this is:
$$
\begin{aligned}
V &= \eta V_T \cdot ln\left( \frac{I + I_S}{I_S} \right) \\ \\
&= \eta V_T \left[ ln(I + I_S) - ln(I_S) \right] \\ \\
&= \eta V_T \cdot ln(I + I_S) - \eta V_T \cdot ln(I_S) \\ \\
\end{aligned}
$$
When \$I\$ is significantly greater than \$I_S\$ (which is likely, \$I_S\$ is typically sub-picoamps), this becomes:
$$
\begin{aligned}
V &= \eta V_T \cdot ln(I) - \eta V_T \cdot ln(I_S) \\ \\
\end{aligned}
$$
Here you might see the problem; that is not a logarithm, it's a sum of logarithms. The term \$\eta V_T \cdot ln(I_S)\$ is significant, but is thankfully constant. Still, it must be accounted for in the log-antilog system.
With saturation current \$I_S=10fA\$, and thermal voltage \$V_T=25mV\$, this term is:
$$
\begin{aligned}
\eta V_T \cdot ln(I_S) &= (25\rm{\ mV}) \cdot ln(10{\ fA}) \\ \\
&= -0.8\eta
\end{aligned}
$$
Diode ideality factor \$\eta\$ might also be a problem, and for my argument here I'm going to suggest replacing diodes with diode-connected transistors, for which \$\eta \approx 1\$:
simulate this circuit – Schematic created using CircuitLab
Now we have the following relationship:
$$ V = V_T \cdot ln(I) + 0.8 $$
For the input log amplifiers, input current \$I\$ is determined by the input resistances \$R_1\$ and \$R_2\$:
$$
\begin{aligned}
I_1 &= \frac{V_{IN1}}{R_1} \\ \\
I_2 &= \frac{V_{IN2}}{R_2}
\end{aligned}
$$
Therefore the output of those two log amplifiers is:
$$
\begin{aligned}
V_{LOG1} &= -\left(V_T \cdot ln\left(\frac{V_{IN1}}{R_1}\right) + 0.8 \right) \\ \\
&= -V_T \cdot ln\left(\frac{V_{IN1}}{R_1}\right) - 0.8 \\ \\
V_{LOG2} &= -V_T \cdot ln\left(\frac{V_{IN2}}{R_2}\right) - 0.8 \\ \\
\end{aligned}
$$
From there it's clear that we'll have to deal with those 0.8V offsets somehow.
For the antilog stage, with input \$V_{LOG}\$, we have input current determined by the diode:
$$
\begin{aligned}
I &= I_S\left( e^{\frac{V_{LOG}}{V_T}} - 1 \right) \\ \\
&= I_S e^\frac{V_{LOG}}{V_T} - I_S \\ \\
\end{aligned}
$$
The op-amp will invert and scale that current by a factor of R6:
$$ V_{ALOG} = -R_6I_Se^{\frac{V_{LOG}}{V_T}} + R_6I_S $$
To obtain the anti-log of \$V_{LOG}\$, that input will need to be scaled first by a factor of \$V_T\$, and there's another annoying offset term \$+ R_6I_S\$ to be accounted for.
The log amplifier output voltage is already scaled by \$V_T\$, which you'll see by rearranging its equation a little:
$$ \frac{V_{LOG}}{V_T} = -ln\left(\frac{V_{IN1}}{R_1}\right) - 0.8 $$
The term \$\frac{V_{LOG}}{V_T}\$ in the anti-log equation is therefore already taken care of, and the anti-log stage won't need to scale any further.
Furthermore, the offset term \$+R_6I_S\$ in the anti-log equation is also already accounted for by the 0.8V offset in the output of the previous stage, so that also can be ignored.
Consequently, if you were to cascade a single log stage and an anti-log stage, the system would actually work. That is, input and output voltages should be the same:
simulate this circuit
In this single-input implementation, there is no need to invert. I simply reversed diode polarity in the anti-log stage to account for the inversion of the log stage.
If I sweep input \$V_{IN}\$, output \$V_{OUT}\$ follows nicely:
The problem arises when two log amplifier outputs are summed. There are additional 0.8V and \$R_6I_S\$ offsets that must not be presented to the anti-log stage. This offset will scale the output by many orders of magnitude, causing output saturation. Your summing stage can be employed not only to invert and add, but also to remove those pesky offsets. That's done by V3 and R7 here:
simulate this circuit
The choice of 660mV for V3 happens to be the voltage across the diode with 1mA through it, and the reason for this lies in the algebra somewhere. I'll leave that up to you to figure out. Suffice to say that this value determines what the log-antilog system considers to be the unit, 1.
Instead of calculating this offset by hand, and providing a fixed voltage source V3, you can employ another op-amp to produce the exact required voltage offset automatically. That's the stuff in the blue box here:
simulate this circuit
