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I have a few simple question about MOSFETs on how to interpret their symbols and how the pins and gate voltage are defined.

• I see symbols with the Source shown on the top and Drain on the bottom, and vice versa. Normally on I’d tend to assume that the top pin is considered positive with respect to the bottom pin (unless indicated otherwise). However, given they’re shown both ways up, does this mean that MOSFETs can be used in either configuration?

I assume this is the case as I’ve seen circuits with transistors in both configurations, e.g. inverters where the PMOS Source is positive w.r.t. its Drain, and the complementary NMOS Drain positive w.r.t. to its Source.

• MOSFETs will turn on or off depending on the Gate-Source voltage (VGS). When interpreting VGS, should I always consider the voltage between the pins labelled Gate and Source, regardless of whether the Source is positive or negative w.r.t. to the Drain? In other words, does the pin considered the “Source” remain fixed, or does it depend on how the MOSFET is connected?

• Finally, for an enhancement mode PMOS, VGS must be negative for the PMOS to conduct. Am I correct in saying that VGS must be negative, but the voltage applied to the Gate does not necessarily itself need to be negative? For example, if the Source is at +5V and the Gate is at 0V, then VGS is -5V and the PMOS should conduct?

Thanks in advance for any advice!

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1 Answer 1

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However, given they’re shown both ways up, does this mean that MOSFETs can be used in either configuration?

Not usually. The parallel body diode within the MOSFET will heavily conduct if for example positive is applied to the source and negative applied to the drain in an N channel MOSFET: -

enter image description here

Image from What is semantics behind BJT and MOSFET transistor symbols?. The body diodes are explicitly shown in the image above.

When interpreting VGS, should I always consider the voltage between the pins labelled Gate and Source, regardless of whether the Source is positive or negative w.r.t. to the Drain?

Yes you should.

In other words, does the pin considered the “Source” remain fixed, or does it depend on how the MOSFET is connected?

The source may be attached to a power rail or, the MOSFET may be configured as a source follower (in which case the source is the output and you might need special drive circuits to activate/deactivate the MOSFET). A prime example is a push-pull half-bridge that uses two N-channel devices. The one at the bottom has its source grounded but, the one at the top is a source follower and requires special drive circuits to obtain full performance: -

enter image description here

Image from Design Fundamentals of Implementing an Isolated Half-Bridge Gate Driver (Analog Devices).

for an enhancement mode PMOS, VGS must be negative for the PMOS to conduct. Am I correct in saying that VGS must be negative, but the voltage applied to the Gate does not necessarily itself need to be negative? For example, if the Source is at +5V and the Gate is at 0V, then VGS is -5V and the PMOS should conduct?

Correct.

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