Besides the reason that electron mobility is higher than hole mobility, what are the other reasons of preferring an N-channel over a P-channel MOSFET?

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    \$\begingroup\$ are you asking about discreet devices or in IC processes? A correct answer here will involve the subtle aspects and process differentiation. \$\endgroup\$ – placeholder May 31 '13 at 15:58
  • \$\begingroup\$ Cost, availability, performance, lower resistance, higher current capability, easier control, etc... But as mentioned, the right answer depends upon the application. \$\endgroup\$ – Kurt E. Clothier May 31 '13 at 18:10
  • \$\begingroup\$ Also, NMOSFET can be used as low side switch, & I found it easy to trigger NMOSFETs than PMOSFETs. \$\endgroup\$ – Deep Feb 11 '18 at 6:46

Since you haven't specified I will choose my domain of answer: chip design.

The answer really depends ... NMOS is not always better than PMOS in all areas.

Carrier mobility:

  • most modern CMOS processes are on <100> crystal orientation wafers. In this system since the transistors are in a common substrate there will be a ~ 2.2X factor in mobility between electrons and holes.

    • however, when they are separate devices like discreets, a different crystal orientation could possibly be used so the mobility argument will be weakened (but electrons will always have better mobility than holes).
  • processes around the 65nm node started using stress/strain to more closely match the mobility between the two type of transistors, mainly for size savings. Intel is a prime example of this approach.

Substrate connection:

  • Most CMOS processes are on P-type wafers with dual well implants. That means that NMOS transistors have all of their wells at the ground potential (unless they are triple well processes). That means that the bulk connection for a unity gain follower using a NMOS device will be at ground and the back gate effect will be present that reduces the gain to ~ 0.8. When implemented with PMOS devices with the bulk connection tied to the source, the gain can be 1.0.


  • PMOS transistors at process nodes above 0.35u were typically buried channel devices (due to process techniques used at those nodes). these devices had much lower noise than NMOS transistors in the same process node. Simply because the channel was kept away form the Si/SiO2 interface states at the Si - Gate Oxide boundary. This is particularly true of flicker noise.

  • PMOS transistors below 0.25u mostly were surface channel devices and as a result they picked up NTBI (Negative Temperature Bias Instability) noise like characteristics.

Process variability:

  • because of the larger sizes required to match the \$G_m\$ PMOS devices are larger and therefore are better matched with fewer effects from LER (Line Edge Roughness).
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Why n-channel MOSFTs are better then p-channel MOSFETs?

The only real reason is that electron mobility is higher than hole mobility. All of the physical advantages fall out of that (gate-capacitance, channel resistance, cost, size, thermal rating, etc)

Every other difference is just a difference. Let's consider polarity. If you are using the transistor as a switch, p-type is "on" under conditions opposite those of the n-type.

This is analogous to a push-button being normally-open (push the button to close the circuit -- typically that means turn something on) and normally-closed (push the button to open the circuit -- typically turn something "off").

Which of these behaviors is better in your application, depends on the application.

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N-channel FETs have electrons as their current carriers which have high mobility thus the drain current is comparatively high ; here the input noise is low and the transconductance is large . Whereas for p-channel FETs, they have holes as current carriers which have comparatively less mobility than electrons thus making less drain current to flow ; here in this case the input noise is more and transconductance is small.

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