I have a parameterised module in verilog, where the parameters are a clock rate and refresh rate, which is used to calculate how many cycles of inactivity are inserted between instances of a repeating operation. However, it is very easy to set parameters that cannot be attained (because the operation takes a non-trivial length of time, so the repeat would have to occur before it had completed), and at the moment the design does not give any feedback on this.
I was wondering if there was some way I could trigger an error during synthesis (or compilation prior to simulation) if the conditions cannot be met (i.e. if one localparam is less than another)? Some equivalent of the popular C/C++ compile-time-assert hack, perhaps.