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I can't post a picture so the question will use Boolean Algebra. For me an SR Latch is

S NOR Q' = Q
R NOR Q  = Q'

I will represent Q' as P since Q' might be mistaken as NOT(Q).

S NOR P = Q
R NOR Q = P

If I want to turn it into a circuit using only NAND gates it turns into

NOT(NOT(S)*NOT(P))
NOT(NOT(R)*NOT(Q))

When I build the circuit it seems that I have way too many NAND Gates. Random pictures online show that I only need 2 NAND gates. This does not make sense to me, specially if it can be built with 2 NORS then with Boolean algebra I should get 8 or 6 NANDS.

That is what I came up with, which happens to reduce to 4 NAND gates. Is that correct?

enter image description here

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  • \$\begingroup\$ 1. Note that in the random pictures online that when you build an SR latch with NAND gates the inputs are \$\overline{S}\$ and \$\overline{R}\$ not \$S\$ and \$R\$. 2. Q' is NOT(Q), so NOT(P) is Q and NOT(Q) is P. \$\endgroup\$ Jun 1 '13 at 2:22
  • \$\begingroup\$ Yes, Q' is NOT(Q). \$\endgroup\$ Jun 1 '13 at 3:21
  • \$\begingroup\$ If you still want a picture, you can post a link here and someone will edit it in as an image. \$\endgroup\$
    – user17592
    Jun 2 '13 at 6:42
  • \$\begingroup\$ Good idea. I just added it. \$\endgroup\$
    – Mike John
    Jun 2 '13 at 7:06
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enter image description here

S - R (or R S) just means that we use a 'HIGH' or '1' to Set or Reset the outputs. The Set signal should make the Q output high and the Reset signal should make it low. This operation can be done by cross connecting two NOR gates.

Another commonly used circuit is the NOT S R flip flop using NAND gates. Here the controlling input is a 'LOW' or '0' i.e. NOT '1' This is constructed with two NAND gates.

Now it is possible to construct NOR or NANDS from other gate combinations so that circuit diagrams may look a little different. For example you could add an inverter to the inputs of the NAND version and convert it to an S R type. By connecting the two inputs of a NAND gate you can make an inverter, so a 4 dual input NAND gate (e.g. 4011 or 7400) could be used to produce you S R flip flop.i.e 4 gates, not the 6 or 8 gates you think.

A walk through the circuit operation of the NAND S R flip flop (4 gates).

When both inputs are low the flip flop will be in one of two states, either the Q output is high or it will be low. In either case the low (0) inputs will have no effect and the outputs remain in their initial state. Putting a '1' on input A ('0' on B) will cause a '0' input at C that will produce a '1' output at E (because any '0' input on a nand gate will produce a '1' output. The E output will place a '1' input onto the bottom gate. The other input is also '1' because the B input is '0'. The output of the bottom gate will then go to '0'. This '0' output (F) will keep the top gate output at '1' when the A input changes back to a '0'. The flip flop is now in the SET condition. (a '1' on the SET input has produced a '1' at the Q output)

Similarly if the B input is a '1' (A input '0') this will put a '1' at the F output. ,This will produce a '1 on the input to the top gate that combines with the other '1' at C to produce a '0' at the output. This '0' will keep the bottom gate output at '1' when the B input goes to '0'. The flip flop is now in the RESET condition. (a '1' on the 'REST' input has produced a '0' at the Q output)

As with all S R flip flops a problem arises when you try to SET and RESET the outputs at the same time. In this case both outputs will go to '1' and it will depend which input falls to '0' first as to how the state of the outputs will be determined. enter image description here

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  • \$\begingroup\$ Yes I can invert the NOT S & NOT R. Still, can you prove to me that it will provide the same result? \$\endgroup\$
    – Mike John
    Jun 2 '13 at 6:40
  • \$\begingroup\$ @MikeJohn I've added a little bit extra on the answer just for you. \$\endgroup\$ Jun 2 '13 at 12:37
  • \$\begingroup\$ That is exactly what I needed for clarification. \$\endgroup\$
    – Mike John
    Jun 2 '13 at 17:08

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