# Do I need to terminate extremely short traces (< 0.5 inches)?

Some background: I have a little hobby project running that basically interfaces a 64 pin ARM mcu (the STM32F405RGT6) to a stereo codec (a TI PCM3010) via I2S interface. I'm deriving the master clock for the I2S bus from the MCU (the stm32f4 series apparently has a PLL for this purpose), which runs at 12.288 MHz (256 times the sampling frequency, which in this case is 48kHz). The bit clock and respective data in/data out lines run at approximately 3MHz. I'm currently looking at routing the design on a 2 layer board, since it doesn't really have a huge amount of I/O. So far I've been able to locate the codec literally right next to the MCU, so that trace lengths to respective pins are 3 to 13mm in length (and as a plus, the analog/digital halves are nicely segmented). The ground plane is unbroken, except where I have to use a via for the data out line.

Now for the actual question; is it even required to terminate transmission lines under a certain length? I've seen in some literature that this is case (as in you don't have to terminate anything), but why is this exactly? I know it really depends on the edge rate (and source/destination/trace impedance), but would I gain any benefits by doing it anyway? Due to the layout of the codec chip, it would be possible to series terminate the lines, but really only by moving it further away, and by introducing more vias and broken ground planes into the equation. I realize this is a sort of low speed/edge rate design and I could get away with routing the board with my eyes closed, but I'd actually like to design something properly for once!

• Do you know what your track characteristic impedance is? Have you designed it to be consistent? Will the chips driving the line cope with a 50 ohms termination without destroying logic levels? If no then you can still get some benefit with a 50 ohm terminator in series with (say) 10pF. – Andy aka Jun 1 '13 at 15:41

First, as you mention, the critical parameter is usually the rise and fall times of your edges. You can estimate the effective "frequency knee" of your signal by

$f = \dfrac{\alpha}{t_r}$

where $t_r$ is the faster of your rise and fall times. The parameter $\alpha$ is a kind of fudge factor; it depends on whether you measured the rise time as a 10%-90% or a 20%-80% value, and some authors give numbers between 0.5 and 0.8, but to be safe you could just use 1.0.

As Jippie discusses in his answer, if the wavelength associated with this frequency is more than 10x the trace length, you generally don't need to worry about transmission line effects.

And in fact this is just how most CMOS and TTL drivers are intended to operate---except for certain specific types, they don't really have the current drive capability to drive a termination resistor of 50 or 75 Ohms.

Another complication is that most CMOS and TTL devices won't have a spec for rise and fall time. You'll have to estimate it from the drive current capability and the load capacitance:

$t_r \approx \dfrac{(V_h-V_l)C}{I}$

Where I is the short circuit output current for your driver and C is estimated from your track geometry and the input capacitance of the load.

If you are using ECL parts, be aware that even if you don't terminate the transmission line, they still need a pull-down resistor to properly bias the output transistor.

• Judging from the formula posted, I think I'll take a chance and just leave them un-terminated. The specifications about the output drivers on this chip are somewhat vague, and really only state that they're apparently 'high current'. The slew rate on these drivers is adjustable, so I can probably fiddle with that if I run into excessive ringing (not that I actually care actually care about EMC, since this is just a DIY thing - it just feels nice to do things properly :) ). – Adam Jun 4 '13 at 12:42

Rule of thumb is that transmission line theory comes into play when the length of the transmission line is 10% or longer than the wavelength of the signal.

The wavelength of the signal can be calculated as follows:

$\lambda = \dfrac{c \cdot v_p }{f}$

Where:

• c is the speed of light (299792458 m/s)
• vp is the velocity factor. This factor is a constant given for the material you are using. Rule of thumb for generic coaxial cable is 70 or 80%, similar numbers are available for PCB tracks and some EDA tools have built a built in calculator for finding this factor. $\small{\text{(kudos @ThePhoton for finding the correct name and reference)}}$
• f is your maximum frequency.

So for example if you have a 1MHz signal in an average coaxial cable, the wavelength $\lambda = \dfrac{299792458 × 0.7}{1000000} = 210 \text{m}$. Again as a rule of thumb, when using a 1MHz signal and if your cable is shorter than 20m, you don't have to worry too much about impedance matching.

Of course when you are getting results close to the rule of thumb, you should pull out more accurate formulas. @ThePhoton makes couple good points in his answer.

• Does this apply if you have a fast edge ? For instance, if I have a 1ns rise/fall, yet my signal is only 1Mhz, is the above rule of thumb true ? – efox29 Apr 5 '15 at 8:12
• @efox29 A fast edge is composed of higher harmonics, integrer multiples of the base frequency (1MHz in this example). The sharper your edge the more high harmonics in the signal. If you want to preserve these edges, you'll have to account for those high frequencies and thus the 10% rule of thumb would relate to the highest harmonic you have in scope. You should consider either proper impedance matching or you may get away with a low pass filter to shave off the sharp edges. – jippie Apr 5 '15 at 9:23
• Makes sense. Is that a common occurrence to LPF a signal to keep signal reflections at bay for fast edges ? – efox29 Apr 5 '15 at 9:33
• Not sure. It might work well enough the reflections cause problems, but it is better to use proper termination. (cc: @efox29) – jippie Apr 5 '15 at 15:19

## protected by KortukJun 1 '13 at 19:54

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