LDOs have a "reference input" pin, which is often called "ground". The internal voltage reference and thus the output voltage are referenced to this pin.
If the LDO's "ground" pin is placed on a noisy ground (like next to a switching regulator) then the LDO will attempt to reproduce whatever noise comes into "ground" into its output.
Likewise, the LDO's output cap creates a HF short circuit between its "ground" and "VCC" sides.
So if you put the LDO in a place where the ground is noisy, you'll get the same noise in the output. Thus it is better to put it at the point of load, next to the ADC. If the ADC has a "negative reference input" (doesn't matter if it is called something else like "ground") then putting the LDO and output cap next to it is optimum.
The LDO's input cap, which needs to be next to the LDO for stability, will inject noise into ground too. That's a good occasion to put a resistor or ferrite bead in series with the supply from the SMPS to avoid this, and it also gives better HF PSRR.
Note LDO datasheet PSRR is specified at a certain dropout voltage. If dropout is too low in your application due to input voltage being too low, then the PSRR degrades significantly because the pass transistor doesn't have enough headroom to operate. So if you pick a LDO with sexy datasheet PSRR curves at a dropout of 1V, you will get what the datasheet says for a dropout of 1V or more, but if you operate it with a dropout of 0.3V, who knows what you will get.
If your ADC draws varying current from the analog supply or reference, then the LDO's transient response to that current variation also matters. Any "low noise" voltage from which a varying current is drawn may no longer be "low noise".
