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Respected readers, I am working with a totem pole PFC circuit. In an experimental study, I face a problem of high-frequency notches in source voltage (Yellow one). I found an explanation behind this. It happens because of source inductance, which gives an L(di/dt) effect at the switching frequency. Is this problem inevitable or is there a solution for it? Please give me a suggestion for it. I will be thankful to you.Yellow one is the input voltage profile

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    \$\begingroup\$ Are you using GaN FETs for the high frequency switches? If not, the reverse recovery losses and spikes/EMI are horrific for the body diodes of conventional FETs in a totem-pole PFC. A schematic and more details may help get a better answer. \$\endgroup\$
    – John D
    May 15 at 16:41
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    \$\begingroup\$ Show the schematic and the points you get the measurements across. \$\endgroup\$ May 15 at 16:44
  • \$\begingroup\$ The layout might be helpful as well- Using integrated driver/FET GaN can help, or at least GaN FETs with Kelvin connections to the source for the driver. But in the absence of a schematic and layout it's difficult to do anything but make general suggestions. \$\endgroup\$
    – John D
    May 15 at 16:51
  • \$\begingroup\$ Please post schematics and indicate scope probe locations. Photos are also helpful. Is this a real-world measurement, or a simulation? \$\endgroup\$ May 15 at 21:49
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    \$\begingroup\$ It's not obvious what's causing your input spikes, but a totem-pole PFC requires a very careful layout on a PCB, minimizing parasitics. It also requires careful gate drive signals and timing. Until you have those things as a starting point it will be hard to optimize performance. A gate driver far from the FET hooked up with jumper wires is not a good way to prototype a PFC. \$\endgroup\$
    – John D
    May 16 at 16:24

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