Selectively Activated External Circuit for ADC Measurement

Question

I'm looking for efficient yet simple-to-integrate solutions where analog signal outside of microcontroller's range is being measured (e.g. 12V power supply) and measurements are done selectively. This means a conductive path being measured would be switched on before measurement and switched off afterwards to prevent unnecessary power loss in a battery-powered application.

OPTION 1:

The simplest method would be a resistor divider with a low-side switch and a two wire measurement:

^{simulate this circuit – Schematic created using CircuitLab}

Temporarily driving EN node then differentially measure divider signal in order to effectively cancel the effect of non-zero \$V_{DS,ON}\$. This requires 3 signals to be controlled by MCU, preferably there would be only two.

OPTION 2:

This might be considered an upgrade of previous method in case of using a MCU. Low-side switch is replaced with GPIO output - when measuring driven LOW, when not it would be driven HIGH. However one drawback that comes to mind is whether MCU digital pin is destroyed when MCU digital output is set HIGH to disable current flow through resistor divider. This would pull MCU pin to, say +12V, and even though this pin would be configured to high-Z before disabling current source through MCU output pin.

OPTION 3:

Another straightforward method is current measurement using op-amp:

^{simulate this circuit}

This way is more convenient if as only two signals are used by MCU. Its less convenient since each measuring point (expecting multiple) needs a single op-amp.

Another way might be the switched-capacitor circuit which I haven't dealt with before. What I'm also interested in is whether any such integrated circuit solutions exist for a single channel component (like 3 or 4 pin package). And whether better, more efficient methods exist in case of using discrete components where focus is a low-power selectively activated measurement which is also signal-level independent.

EDIT:

The following Spice simulation is giving me the results I want. The assumption here is that \$V_{gs,th}\$ is low enough that a 3.3V MCU output may sufficiently open NMOS with negligible error due to non-zero \$V_{ds,on}\$ voltage. Although intended for a low power application, I selected a \$1mA\$ current as the drain current during measurement phase to sufficiently open the NMOS. I don't see mayor drawbacks with this approach except to minimize leakage current when NMOS is closed.

The approach with current sensing might work as well. A low cost solution would include INAx180 current sensing amplifier. The only problem in terms of low-power aspects is that both current sense and amplifier IC would have to be switched off during non-measurement period.

I welcome any thoughts on this matter.

Answer 1

This would pull MCU pin to, say +12V, and even though this pin would be configured to high-Z before disabling current source through MCU output pin.

The input protection diodes will shunt the input to positive I/O supply rail. GPIO inputs are only high-Z between the supply rails. As soon as they go beyond rails, either of the diodes starts to conduct. The input will only be destroyed if the current that flows into the pin is beyond the specs of the chip. In your circuit, nothing bad would happen - just waste of slightly less power than if the pin was pulled down to 0V.

This affects both option 1 and 2 - i.e. the only way to really disable a divider that feeds the GPIO pins is to disconnect the ends that are beyond I/O rails. Say a divider between -5V and +12V would have to have both ends disconnected to prevent a current flowing into or out of a GPIO/ADC pin.

[Option 3] is more convenient if as only two signals are used by MCU. Its less convenient since each measuring point (expecting multiple) needs a single op-amp.

Op-amps come in speck-of-dust-sized packages, so that's not that big of a deal. And they are cheap and take very little power. But most of them have their input range limited to the rails. So a micro- or nanopower op-amp running from 5V will also take current from a "disconnected" divider.

Another way might be the switched-capacitor circuit which I haven't dealt with before.

That is indeed an option one could explore.

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Let's see if we could make a "fusion" approach work:

^{simulate this circuit – Schematic created using CircuitLab}

NMOS switch M1 is controlled by a 3.3V GPIO signal. It, in turns, controls a high-side PMOS switch M2. When M2 turns on, it charges the reservoir capacitor C1, from with an ADC reading can be taken. A measurement cycle lasts about 1ms due to the long RC time constants, but the current consumption is very low.

The \$V_{DS,ON}\$ voltage due to \$R_{DS,ON}\$ is negligible, since the mosfets used have channel resistance <10Ω relative to the 0.1MΩ resistance of the divider network.

The capacitance of C1 may need to be brought up an order of magnitude 10nF to minimize the sampling glitch of the ADC's front end. You'd need to compare the divider voltage to ADC measurement to see where the diminishing returns begin.

A bench multimeter with High-Z input option (i.e. \$Z_{IN}\gg 1{\rm\,G \Omega}\$) is needed to make the measurements due to relatively high source impedance of the ADCIN node. Otherwise, you'll need a buffer op-amp to make measurements with a typical 1..10MΩ voltmeter input.

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Since the voltage measurement circuit really sips power, you'll want to have a common enable line for all the circuits. They can be turned on, and after a timer expire, a series of ADC measurements is done in quick succession on all of them. Then they get disabled.