I have been studying a cascode current mirror for an electronics class, that follows this configuration:

Cascode Current Mirror

As I increase the output voltage Vd4, for most of the sweep the behavior is as expected, but for higher voltages, the current increases (I assume due to channel length modulation, CLM), but I can't really understand how it does not follow the saturation equations (already taking in account for CLM, and using previous estimates from studying the regular current mirror). The plot of the current can be seen below.

Full plot of the DC Vd4 sweep

Here is a detail for higher voltages.

detail of the DC Vd4 sweep

  • \$\begingroup\$ In which way doesn't it follow? You don't get 10uA? The point where current starts to become constant doesn't coincide with the equation? \$\endgroup\$
    – Designalog
    Commented May 17 at 19:48
  • \$\begingroup\$ Actually both. It doesn't follow the equation (at least the first order one), and the current is not the same in MN4 and MN2. Even the channel length modulation doesn't explain the increase. \$\endgroup\$ Commented May 18 at 17:12
  • \$\begingroup\$ Unless you're designing for with 1um long transistors or bigger, forget about fitting the textbook saturation equation anything that is submicron technologies. Use the EKV model instead, but you have to do a fitting first. \$\endgroup\$
    – Designalog
    Commented May 18 at 17:39

1 Answer 1


What you're seeing there is drain-bulk leakage in MN4. You can infer this by comparing the currents you plotted: Iout goes up while Id2 remains roughly constant. This means that the additional output current isn't flowing "down" through the cascode (through MN2) but instead takes a shortcut by flowing directly into ground through MN4's bulk terminal.

It seems like your MOSFETs aren't really made for analog operation at 3.3V.


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