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I need to generate a VLSI Systolic array to implement the AES encryption algorithm with key length of 128 bits. Following are the possible ways :

  1. Systolic for Key expansion
  2. Systolic in MixColumn
  3. Systolic for the on-the-fly calculation of S-box

For option #3, I am referring to this paper. Figure 2.1 from this paper gives the steps for calculating multiplicative inverse, which is the first step in S-box calculation. I am trying to convert this diagram into a systolic array, but haven't reached a concrete solution until now.

I am also referring to this paper to convert a cyclic algorithm into a Systolic one. However, I am not able to convert the operations involved in the AES encryption into Systolic structure. Could anyone give me any pointers on how to approach this problem?

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    \$\begingroup\$ This is a perfectly reasonable digital design implementation/architectural problem. You state this is a VLSI problem - that can mean different things to different pople. Is this an FPGA solution acceptable or perhaps you need to do directly to a ASIC design flow? \$\endgroup\$ – placeholder Jun 2 '13 at 22:30
  • \$\begingroup\$ @rawbrawb : First, it has to be implemented and synthesized on FPGA. And after verifying the timing simulation on FPGA it has to be transferred to ASIC. It means final implementation is on ASIC. Hence, I have to avoid use of memory as far as possible. That is why I am trying to do on-the-fly calculation of S-box. \$\endgroup\$ – Amruta Jun 12 '13 at 18:36
  • \$\begingroup\$ Why can't the ASIC have memory? \$\endgroup\$ – Michael Fox Oct 26 '14 at 19:36
  • \$\begingroup\$ @Amruta please take a look at this question \$\endgroup\$ – RinkyPinku May 1 '15 at 6:14
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There have been papers published on AES implementation using systolic arrays, e.g. "The AES in a systolic fashion: Implementation and results of Celator processor" (2008), but it does use some memory. Another is "An 8-bit systolic AES architecture for moderate data rate applications" (2009), basically a mix column design. Whether any of those approaches meet your other (rather unclear) design requirements, I don't know.

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