im building a dc-dc converter using center tapped transformer.

The issue i have is ringing on mosfet drains staying through whole half wave. The voltage on capacitors on secondary side rectifier seems right according to turn ratio, but im worried that the ringing will kill the mosfets. Since even at relatively low loads the voltage spikes to over 50V (converter will be supplied with 12V) which is the rating of TVS diodes i put across mosfets and it makes them hot very quickly. I want to solve ringing issue before i try higher loads, since im afraid that TVS diodes could burn and the spikes would kill the mosfets (they are rated for 75V). The converter will be running 2 transformers with pirmaries in parallel which i suppose will make ringing issue even worse so for now im trying with just one and running converter off 2s lipo battery to reduce ringing voltage. Driver part is supplied with separate 3s lipo battery, 2s one is just for transformer, so drivers get enough voltage and hopefully voltage spikes won't interfere with driver part. 40W light bulb

100W light bulb

On the pictures blue channel is gate waveform, yellow is capacitor voltage (through 1:100 resistor divider) on secondary side, and purple is drain voltage. First picture is with 40w light bulb attached as a load, and second one have 100w one instead. As you can see such minor loads (in comparison for few kW which inverter will be meant) could already make drain voltage raise to levels which makes TVS diodes hot. In other topic someone suggested to increase frequency to that ringing frequency (right now its running at around 100kHz). I tried to raise frequency first to around 180kHz and later to around 250kHz but i dont think i can raise frequency even higher to ringing frequency which should be around 1MHz. The sg3525 i use cant generate such frequency, but even if it could i dont think its a good idea to use such high frequency for this purpose. The frequency raise lowered the ringing amplitude only a little bit, nowhere near enough, and ringing freqency stayed the same. The driving circuit is just an sg3525 connected to 2 mosfet drivers with 0.47ohm gate resistors. It is driving 2x8 IRF2907ZPBF mosfets which are connected to 3x20mm copper bars to which the transformer is screwed. The transformer is using B65684A0000R027 EPCOS core and is wound with 1:20 ratio using 2 5.5mm diameter litz wire as a primary which consists of single turn for each side, and 20 turns of thinner litz wire as secondary. I tried to make connections as short as possible and tried adding RCD sunbbers (10uF, 0.2ohm and 150v 30a shottky diode) but the sunubbers only helped a very little. All solutions i tried only helped in very minor way and increasing the load very slightly completly negate their effect. I imagine connecting much higher loads, even third of what the inverter should be rated to, would instantly kill the TVS's and the mosfets.

If you can think of any solutions i'll be more than happy to read and try them, since im completly out of ideas. I invested quite a bit of time and money for designing and building the converter and i don't want to give up on it. Any help will be appreciated. I don't need drain waveform to look perfectly square, i just want the voltage low enough to not kill any of components.

Edit: Here im posting schematic diagram, i had to add changes on it so sorry for inconvinience while looking at it.

enter image description here

This pics show the transformer and a pcb.

enter image description here

enter image description here

Here is primary winding diagram of transformer:

enter image description here

  • \$\begingroup\$ Show the schematic. \$\endgroup\$ Commented May 22 at 21:26
  • \$\begingroup\$ Please show a winding diagram of the transformer: how many turns, what wire size, what layers/order, wiring to pins, etc. \$\endgroup\$ Commented May 22 at 21:48
  • 2
    \$\begingroup\$ That thing is way too big physically. It needs to be compact - you have a huge current loop. The PCB layout needs to be redone, and the transformers need to be right on that PCB. The mosfets should be a spine in the middle of the board, with two short wires going to the transformers sitting on either side of that spine. The PCB needs to have 6-8 layers ideally, 4 layers minimally. There are no capacitors in sight that would close the current loop. As shown, this has about zero chance of working. \$\endgroup\$ Commented May 22 at 23:07

2 Answers 2


The centre-tap topology will always cause this voltage over-shoot & ringing, due to fact that there will always be some leakage inductance between the two primary windings. There are only two ways to control such ringing:

  1. Snubbers, of which there are several types.
  2. Change the topology, again there are several types to choose from.

What power level are you designing for?

UPDATE 2024-05-25

Here is the first idea I would suggest to try in your current situation:

Add voltage clamps to constrain the maximum voltage across the MOSFETs to a reasonable level.

This is a relatively simple add-on. However, given the parasitics of your circuit seem to be quite large (for various reasons which can be explored later), the power that will be processed by these clamp circuits will also be quite large relative to the output power of the converter. Nevertheless, this is a good approach if you want to continue using the existing design with minimal changes, which will reveal what practical maximum power level it may achieve. It may also expose the limitations of the existing design, and suggest the next steps to a more refined design.

Voltage Clamp, Option 1: Dissipative.
This is one of the simplest voltage clamp circuits. The diode catches the peak of the MOSFET Vds waveform and clamps it to the voltage on the capacitor. Some energy is transferred to the capacitor in this part of the cycle. When Vds goes below the clamp voltage, the charge stored on the capacitor is then drained away by the resistor. The other end of the resistor can be connected either to GND, or to the positive supply rail, the latter option may be more efficient in some circumstances.


simulate this circuit – Schematic created using CircuitLab

There are other voltage clamp options, the next being one where the resistor is replaced with a power converter to return the energy to either the supply or the load; however, there is no point pursuing that option until we have a clear understanding of exactly how much power is required to be captured by the votlage clamp.

Design Considerations
The supply voltage is 12V, the MOSFETs are rated at 75V, and the TVSs are rated at 40V (the 5KP40A starts conducting at 44V, and clamps to 64.5V at a maximum pulse current of 79.1A). I suggest targeting a maximum clamp capacitor voltage of about 3 times the input voltage, ie: 36V, as a starting point, and seeing how much power has to be collected by the clamp to achieve that goal. This voltage is well under the clamp voltage of the TVS, the idea being that the clamp does most of the work, leaving the TVS to "clean-up" any very short voltage spikes that the clamp cannot deal with.

How much power should the clamp capture and dissipate? Well, I would suggest that if the clamp has to handle more than 10% of the power rating of the converter, then the entire converter needs a serious re-design. So, I suggest starting with a power processing capability of about 10% of your converter power rating, ie: 600W (10% of 6kW). This will enable you to determine to what extent the parasitics are affecting the performance of your converter.

Component Selection:
The components shown in my schematic are starting points only for you to evaluate for this application. The diode is the most critical component here: it must be very fast since it must be able to handle very fast current pulses while not contributing significantly more switching loss to the MOSFETs.

I suggest starting with a diode rated for at least 75V (the same as the MOSFETs) or a little higher, say 100V - keeping this voltage rating low at this stage means improving your chances of finding a suitable diode. The current rating is even more of a guess, since it will be carrying the full load current for a very brief time - the duration of that current pulse will be totally dependent upon (a) switching frequency, and (b) the circuit parasitics, which are an unknown at this time.

You have 8x MOSFETs carrying the load current of a 6kW converter operating from 12VDC. So the input current is about 500A, and each MOSFET carries 62A. Assuming you will have one clamp diode per MOSFET, then based on my experience, the clamp diode will require a continuous forward current rating of between 5% & 10% of this, so 1.25A to 2.5. 2.0A should be OK to start with. Selecting clamp diodes based on surge current ratings is fraught with problems due to the inconsistent way in which the surge ratings are determined. Reverse recovery times should be <100ns, the lower the better. Suggestions to explore:
BYV27-100, 100V 2A 25ns, OEM=Vishay
VS-2EJH01HM3, 100V, 2A, 25ns, OEM=Vishay

This must be high-quality with low ESR, low ESL, and pulse current rated. Typically polypropylene with metal foil windings are used. Metallised film windings may be acceptable, but this will depend on the manufacturers' data. Exact capacitance value is a balance: high enough to be effective, yet not too high that it causes problems at start-up: the inrush of current when the +12VDC is first turned on must not cause damage to any part of the circuit, in particular the clamp diodes. It will suffer the same current stress of the diode, so select based on that. Of course, the minimum voltage must be well above the clamp voltage of 36V, however, most likely you will find that the pulse-current rating requirement will force the selection of suitable capacitors from a much higher voltage range anyway.

Since this is seeing mainly DC voltage plus some ripple, it does not need high pulse ratings. Value should be selected to have a time-constant with the capacitor being several times that of the switching period. Power rating: once the R-value (ohms) is determined, worst-case power dissipation occurs when clamp voltage is constant at 36V.

To ensure good clamping of the MOSFET drain-source voltage, the inductance in the loop formed by the MOSFET, the diode, and the capacitor, must be very low. This means a tight layout is required, and the area formed by these components must be kept as small as possible. In other words: the diode and capacitor must be located very close to the MOSFET pins, and connected with very short wires - preferably just with the trimmed leads of the components themselves. The rule of thumb is: each 1mm of wire adds 1nH of inductance.

The resistor is a slow current path, so its connections to the rest of the circuit can be more relaxed.

  • \$\begingroup\$ Whole converter will be meant for around 6kW. Im not expecting 100% duty cycle, but just around 2 minutes of work and then it can cool down for few minutes, i dont mind that. So im counting around 3kW per transformer at 12V input \$\endgroup\$
    – Kiwi kawa
    Commented May 22 at 22:34
  • \$\begingroup\$ There are 2 Transformers, how are secondaries connected to ensure power sharing? 6kW at 12V is 500A, the layout you have has too much inductance for that high current. If you want a result with this board there are tricks, but they won't be pretty. \$\endgroup\$ Commented May 22 at 23:11
  • \$\begingroup\$ Secondaries will be connected in series making sure they are in phase. Could you tell me more about these tricks you meant? \$\endgroup\$
    – Kiwi kawa
    Commented May 22 at 23:53
  • \$\begingroup\$ I can list a few, but not right now, will come back to you in a few hours. \$\endgroup\$ Commented May 23 at 0:23
  • \$\begingroup\$ I wouldn't be too worried about "one TVS per MOSFET", considering the magnitude of inductances in play here as-is (0.1-1uH). The main thing is the power dissipation will be massive. \$\endgroup\$ Commented May 25 at 0:46

There are several issues with the design and layout, but the most pertinent to the question posed is this:

Leakage inductance is essentially due to the space between windings.

When a PP converter commutates (switches states), the full load current or peak-to-peak voltage must change from one side to the other. This occurs through the transformer's leakage inductance between halves of the primary. Thus, leakage is critical.

Your basic winding geometry for the primary, is two wire pairs overlapped.

It's not clear from your diagram if they lay in side-by-side pairs, alternate (interleaved), or one on top the other (layers):

enter image description here

(To be exact, think of this as the cross-section to the bobbin/transformer winding, revolved around the axis of the core (not shown).)

Of these, the interleaved case has the least stray inductance, acting like a bit more than two twisted-pair cables in parallel. A single twisted-pair is around 0.5 nH per mm of length, so this might be more like 0.2 nH/mm.

If the other options were chosen, the figure will be more like 0.5 nH/mm, or even a little more.

If the diameter of the winding is around 25mm, the circumference is 78mm, so the total inductance in the transformer is around 15.6nH minimum.

Litz wire, is an excellent choice for this project, for purposes of load current: 0.2mm stranding, in that size of wire and winding, will be good to 50-100kHz before losses begin to increase significantly. However, the same effect that makes it good for carrying current, also compromises the leakage inductance: litz is transparent to magnetic fields through the cable, so for purposes of calculating inductance, the wire looks much thinner than it is, and all that space inbetween fills with more magnetic field.

This increases leakage by, perhaps 20-50%, putting the leakage at 18-23nH best case.

So that's the transformer, by itself.

It's not clear how much lead length you have to the transformer; the figures are contradictory: one shows long bus bars and no common point (loose ends), the other short bars (but no supply connection?). Either way, these connections seem to be some 1s to 10s of cm long, and are much more widely spaced than the pairs in the transformer winding, so accumulate inductance even faster. 50 or 100nH here is not at all impossible.

Finally, we can calculate leakage from the waveforms. Given that there are eight IRF2907Z in parallel per side, Coss at the mean ~16V VDS(off) is around 1.1nF, or 8.8nF total. The ringing frequency is about 1.686 MHz, implying \$L = \frac{1}{(2 \pi f)^2 C}\$ or 1.01µH.

These measures differ pretty significantly, so there is likely more that you haven't shown, but in any case the point is clear: stray inductance is wildly too high for the switching rate used here, resulting in significant ringing and overshoot.

  • \$\begingroup\$ Sorry for confusion with transformers, later these long bus bars from center tap will go under the pcb to the back, but for now i connect battery directly to center tap screw to avoid shorting anything while testing. Negative pole of the battery is connected to that U shaped copper bar on back of the pcb. The leads of the transformer are around 10cm in length, . Windings are wound in the way you showed on your 'layered' drawing. \$\endgroup\$
    – Kiwi kawa
    Commented May 23 at 11:23
  • \$\begingroup\$ Ok. Battery lead length is also critical, and that explains the rest. You need a bunch of bypass capacitors to the CT, right at the PCB, and minimal leads to the transformer. \$\endgroup\$ Commented May 23 at 12:27
  • \$\begingroup\$ Seems like i'll have to design a new pcb. Do you think staying with push-pull topology is a good idea, or since i'll be making new design should i change it? Also if i want to keep transformers on pcb, do you have any solutions to creating such high current traces? I assume soldering copper bars onto pcb would warp it, and make soldering mosfets a pain. I also was thinking about increasing input voltage to 24V (2 car batteries in series) or maybe even 48, but id rather have not more than 2 batteries. Do you think increasing input voltage is good idea? I'll rewind primary for that of course. \$\endgroup\$
    – Kiwi kawa
    Commented May 23 at 13:56
  • \$\begingroup\$ Higher voltage is definitely a plus, yes. It solves multiple issues at once. Push-pull is fine for low voltages, as the current is spread out between two legs; compare half-bridge (the inverse situation, reduced voltage / increased current, making it good at high voltages), or full-bridge where you need more transistors in general. You might also consider a modular approach, perhaps with phase interleave to reduce the required size of capacitors. \$\endgroup\$ Commented May 23 at 14:08
  • \$\begingroup\$ Could you please explain the modular approach? It sounds interesting but i never heard of that. Also im not sure if i understand phase interleave correctly. Would it be running transformers lets say 90 degrees out of phase so they cover each others dead time? Should i also reduce number of mosfets by using new ones with lower Rds(on)? It could help to reduce size, but im not sure if i can manage heat in such a small design. \$\endgroup\$
    – Kiwi kawa
    Commented May 23 at 14:44

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