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Are there any flash (or other non-volatile) memories with page erase sizes (in terms of address space) that are not a power of two?

  • I am not interested in old (retro-computing / out of production / one-off custom stuff) memories, but rather stuff that's in production now and available to the public.

  • With respect to page size I am not intending to include things like ECC bits, but just what shows up in the memory space when you read/write data.

  • I am also not intending to include auxiliary stuff like page lock bits or extra fields that may be in a memory and happen to be readable/erasable with special commands.

  • Memories with a total size that is a non-power-of-two size but only supports a full chip erase of the whole memory space also don't count. For example, a small MCU with 196 bytes of flash doesn't count if even if you can only erase the whole thing at once.

  • Stuff like built in flash memory inside a microcontroller counts. But since I am only concerned about the page size in terms of address space, something like a PIC16 micro with 14-bit instruction words doesn't count if the erasable page size is a power of two worth of 14-bit words.

I have worked with many memories over a couple of decades but have never come across one yet that had non power of two erase page sizes. Usually, it's something like 256 bytes or 4K bytes, 64K bytes, etc.

I am designing a generic flash programming algorithm that may be used for several products and I need to know if odd sizes are common enough that I should support them.

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    \$\begingroup\$ A better question would be "Do I need to support non-power of 2 page sizes in flash memories." \$\endgroup\$
    – Voltage Spike ♦
    Commented May 23 at 22:11
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    \$\begingroup\$ @VoltageSpike Probably true, but that's a person determination I will have to make based on how common it is (which hopefully I will know from this question). \$\endgroup\$
    – user4574
    Commented May 23 at 22:28
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    \$\begingroup\$ Flip your question upside down... A) how difficult would it really be to support pages that are not sized by a power of two? B) if you've determined it to be non-trivial, do you care about spending effort to add support for obscure memories, when you don't have evidence of their existence / you can only speculate about them? C) would it be out of this question to revise this algorithm when you encounter a need to support such memories? \$\endgroup\$
    – Attie
    Commented May 23 at 22:31
  • \$\begingroup\$ @Attie Supporting odd sizes basically just uses more bytes in the device description format. If I describe the page using some number N... If I make page_size = 2^N then just one byte probably covers just about any memory that will ever exist. If I try to make page_size = N, then I know I will need at least 17 bits right now (since 64K erase sizes exist) and probably up to 4 or 5 bytes in the coming decades. One set of four bytes is not a big deal, but my challenge is to see how many region descriptions I can pack into a single size constrained network packet, so I strongly prefer 1 byte N. \$\endgroup\$
    – user4574
    Commented May 23 at 22:44
  • \$\begingroup\$ This sounds a little like over-optimising to me, but if you're really that concerned about data size, what about either a variable-size encoding, like EBML's VINT (examples), or a flag to mark 2^N vs N encoding - you could potentially even hijack the concept and use a 1-octet VINT for 2^N (giving a max size of 2^127), and multi-octet VINTs for absolute sizes (if they ever present in the future)... \$\endgroup\$
    – Attie
    Commented May 23 at 23:59

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Given that no one on this site seems to be able to find examples of memories with odd page sizes, the answer appears to be "no, they don't exist".

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The question doesn't seem to mention the interface the bootloader uses to query the attached flash geometry.

Therefore, looked at a sample of standards which have used when creating a driver to query flash geometry for some quad SPI flashes, where different devices used CFI or SFDP to define the flash geometry.

Common Flash Interface

In the JEDEC Common Flash Interface (CFI) JESD68.01 standard, the Erase Block Region Information defines the size of each Erase Block using:

  • A 16-bit field (z)
  • Where erase block within the region is (z) times 256 bytes in size

The examples in JESD68.01 show erase block sizes which are a power-of-two, but the encoding of erase block size in theory allows for erase block sizes which are not a power-of-two.

Serial Flash Discoverable Parameters (SFDP)

In the JEDEC Serial Flash Discoverable Parameters (SFDP) JESD216F.02 standard the erase type sizes are all specified as encoded as 2^N bytes (where N is the Erase Type Size field value). I.e. the erase block sizes are all a power-of-two.

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  • \$\begingroup\$ That's actually good info. Still not evidence that such devices exist, but evidence that CFI at least allows for it. \$\endgroup\$
    – user4574
    Commented May 26 at 17:07

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