# THD of two passive circuits

I am simulating the total harmonic distortion of two simple passive circuits.

VIP_Test = Ideal Sine Wave.

Goal is to find THD for Test1 and OP_VIN_Test. (THD is calculated with the thd function in Cadence Calculator.)

However, as shown in the picture, the THD of the circuit on the right is significantly larger than that of the circuit on the left.

I am not sure as to why the simple passive circuit on the right with ideal res, cap can cause the distortion to significantly rise.

Update:

The frequency of the sine wave is 7 kHz.

The following is the dft of OP_VIN_Test (Red) and VIP_Test (Green).

My guess for the degradation of the thd results is the following:

1. The fundamental tone (7 KHz) has been attenuated by 0.5 due to the frequency response of the circuit, while some of the other lower frequency tones have not been attenuated at all.

This makes the overall THD result larger.

However, I'm not sure why the noise floor is a lot higher (I have set the resistor noise = no) and I'm not sure if this evaluation is correct.

• What's the frequency of your ideal voltage source? Commented May 25 at 5:20
• Please also show how the other harmonics behave for the worst situation. Commented May 25 at 5:34
• @Designalog I have added updates in my original post. I have also included my thoughts there. Please have a look at them and let me know if you agree with my evaluation :) Commented May 25 at 6:59
• Bobflux's answer is the way to go. However, if you want test linearity, the standard way to do so in Virtuoso is to use harmonic balance. Commented May 25 at 7:15
• HB will get rid of initial transients. Commented May 25 at 7:43

Unless you used a special nonlinear model, simulated resistors and caps are perfectly linear and introduce zero distortion. There is no noise either, unless you enable it.

Thus the THD measurement on the left (minus thousands of dB) is not surprising, but the one on the right is way too high.

From the looks of your FFT, it seems you took the THD from the first period:

This is OK for the circuit on the left which contains only resistors. However the one on the right also contains caps, so it will have a non-instantaneous response to the sine wave that suddenly appears starting from t=0. Notice the output signal (blue) is non-periodic: at t=0 it starts at 0V, but after one period it is not back to 0V. So when you apply a DFT, it will generate lots of harmonics.

The solution is to skip enough periods so the circuit has time to settle and the output signal becomes periodic: here I skipped 10 periods. Sometimes more will be needed.

Here's the same, with 0 to 10 periods skipped:

Periods 2 to 10 are not visually distinguishable on the time domain plot, but on the harmonics plot it is clear that each skipped period lowers the harmonics some more, as the circuit's impulse response settles.

--

The 7kHz sine source on the left starts at t=0s, but the one on the right starts at t=1s. This means the right circuit is an identical copy of the left one, with everything is delayed by 1s.

After 1s, the left circuit has settled. So, substracting the output from both circuits reveals the settling tail of the right circuit by removing the output sine wave. That's the interesting bit: the settling tail has no 7kHz component. It looks just like the step response, because it is.

It occurs because the first positive half wave of the sine acts a bit like a step. Unlike all the other positive halfwaves, there is no negative halfwave before it.

I plotted it in log (top) and linear (bottom) for clarity, it shows exponential decay as expected from a RC circuit. So, in theory, settling time is infinite, fortunately it will decay to your favorite tolerance in a finite amount of time.

• Hi bobflux, Thank you very much for your reply. I have tried to increase the settle time (to around 10 cycles) and have made sure that DFT analysis sees complete cycles to avoid spectral leakage (n_sample * Ts = n_cycle * Tsig). However, I'm still not getting low enough THD (currently around -90dB). Commented May 25 at 14:44
• The RC in your circuit has a time constant in the tens of milliseconds... I used 10Hz signal, and it took 10 periods to settle, or 1 second. If you are using 7 kHz then it will take the same time to settle, or 7000 periods. So yes you are seeing a small improvement with 10 periods, but that's not enough... simulated THD tests are very annoying for this reason. Commented May 25 at 17:04
• Hi bobflux, thank you very much. I tried both frequencies (10Hz and 7kHz) with settle periods (10 for 10Hz and 7000 for 7kHz) and they all gave me the result of THD=-6.4kdB, showing the expected results. Thank you very much. I just have one question that I would like to ask. How do you calculate the time constant and the required settle time for the circuit? I thought the circuits have already settled (because there is an output sine signal) and I gave it a few periods before applying dft to complete periods of the signal to measure thd. However, it seems like I didn't wait for long enough. Commented May 26 at 5:37
• You can excite the circuit with a step (input=1V for t<0 and 0V for t>0), plot the transient response, and see how long it takes to settle. If you want to measure THD to -X dB then you can translate that into a maximum distortion voltage that is allowed, and wait until it settles to that. You can plot the transient response using log Y-axis Commented May 26 at 6:19
• The input is not a sine wave, it is a zero signal followed by a sine (ie, a sine multiplied by a step function). There's a discontinuity where the sine starts. For example the first derivative goes from zero to the sine wave's slew rate instantly, so it is not smooth (in the mathematical sense). Anyway, the first positive half cycle of the sine acts a bit like a step. Then as more and more cycles go through the circuit it will "forget" about that step, when that happens it's settled. Commented May 26 at 18:17