Where do I need give my inputs to this three stage master slave flip flop?

Question

In his paper on TSPC logic, professor Razavi talks about use of the following topology as a master slave flip flop

However, I don't know where to give input to this circuit while trying to simulate it in SPICE. I tried using the .ic command to set the input voltage to the left most PMOS to either VDD or 0 since he refers to this node as input node in the paper.

we precede it with a third TSPC stage using a clocked PMOS tran- sistor [Figure 6(c)] and tie the output to the input

where Figure 6(c) is the figure I have added above.

When I simulate it using SPICE with the voltage at X initially set to 0, I get the following results and it doesn't seem like a frequency divider or am I making some mistake here? Is this a sizing issue? since he didn't mention any sizes for these topolgies in the paper (I haven't take a Digital IC Design course yet, so I don't know how to properly size the transistors, so any help regarding the same would also be appreciated)

This is my netlist (I am using GF 180nm Open Source PDK):

** sch_path: /foss/designs/ThreeStageMasterSlaveFF.sch
**.subckt ThreeStageMasterSlaveFF
XM1 net1 A GND GND nfet_03v3 L=0.28u W=0.22u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
+ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
XM2 X CK net1 net1 nfet_03v3 L=0.28u W=0.22u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
+ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
XM3 X A VDD VDD pfet_03v3 L=0.28u W=0.22u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
+ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
XM4 net2 CK GND GND nfet_03v3 L=0.28u W=0.22u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
+ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
XM5 A B net2 net2 nfet_03v3 L=0.28u W=0.22u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
+ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
XM6 A CK VDD VDD pfet_03v3 L=0.28u W=0.22u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
+ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
XM7 net3 X VDD VDD pfet_03v3 L=0.28u W=0.22u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
+ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
XM8 B CK net3 net3 pfet_03v3 L=0.28u W=0.22u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
+ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
XM9 B X GND GND nfet_03v3 L=0.28u W=0.22u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
+ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
Vclk CK GND PULSE(0 3.3 0 0 0 0.25ms 0.5ms)
Vsupply VDD GND 3.3
**** begin user architecture code

.include /foss/pdks/gf180mcuC/libs.tech/ngspice/design.ngspice
.lib /foss/pdks/gf180mcuC/libs.tech/ngspice/sm141064.ngspice typical


.ic V(x)=0
.control
save all
tran 1ns 1ms
remzerovec
write ThreeStageMasterSlaveFF.raw
.endc

**** end user architecture code
**.ends
.GLOBAL GND
.GLOBAL VDD
.end

Answer 1

I can't say what's wrong with your simulation, but the logic should work. And transistor sizing shouldn't be an issue.

The sequence works as follows:

• CK low always forces A high
• on the next rising edge of CK, the combination of CK high and A high forces X low
• on the next falling edge of CK, the combination of CK low and X low forces B high
• on the next rising edge of CK, the combination of CK high and B high forces A low, which immediately forces X high, which in turn forces B low
• on the next falling edge of CK, A is forced high again and the cycle repeats

So X should be toggling on each rising edge of CK.

This does rely on dynamic charge storage — each of the three internal nodes is "floating" (undriven) at some point in the cycle. This requires the gate capacitance to be modeled correctly.

There are also parasitic effects, such as the coupling of the clock signal via gate-to-channel capacitance into the floating nodes, which might overpower the charge stored there. You might try giving your clock signal slower rise and fall times in order to minimize this coupling.

Answer 2

I have found a solution to the problem, apparently according to that very paper itself, TSPC logic fails for clock frequencies below 100 MHz and the clock I was simulating with was just 2KHz. The failure occurs due to corruption of stored states due to transistor leakage currents during excessively long clock periods. I again tested the design with a 1GHz clock and found that it was working as intended.