Ensuring Proper Damping and Protection at Power Connector Inlet

Question

I am designing a power input stage for a system (which consumes up to 90W) and want to ensure it is properly damped and protected. Here are the components and considerations I have incorporated so far:

TVS Diode for Spike Protection: I have placed a TVS diode (SMCJ24CA, DO-214AB) to absorb high voltage spikes caused by ESD or frequent plugging/unplugging of the power connector. Due to design density, the TVS diode is placed 30mm away from the connector.

Series Resistors with Capacitors: I have placed resistors in series with some of the ceramic capacitors to prevent an under-damped LC circuit formed by the external PSU wire, ceramic capacitors, and the power input.

Ferrite Beads for ESD Protection: Ferrite beads are placed between GND and GNDC to provide 30 Ohm resistance, ensuring ESD spikes are diverted back to the PSU ground. GNDC is connected to all connector chassis in the design.

My questions are:

1. Is it acceptable to place series resistors with only some of the capacitors? Are there any potential drawbacks to this approach?

2. Given the space constraints, is locating the TVS diode 30mm away from the connector still effective for ESD protection?

3. For an input voltage range of 12V to 24V, is it appropriate to use a TVS diode with a standoff reverse voltage of 24V? The SMCJ24CA has a minimum breakdown voltage of 26.8V, which I expect to handle spikes above this threshold. The reason behind that that I have a NB693 DC-DC with 28V max voltage for VIN, and I don't want the spikes above 28V to cause over-voltage protection lock (VIN_ALW is connected to the DC-DC's Vin input). The output of the DC-DC is providing power to a BMC that controls the whole design, and it must be very stable for remote server control.

Note: still not sure how the TVS will help the VIN voltage not go above 28V, because the diode I chose has clamping voltage of 38.9V. so it will not stop voltage from crossing 28V, but it will surely redirect the current to GND once we hit the breakdown voltage. I would like some more insight on this issue.

I want to ensure my design considerations are correct and identify any potential areas for improvement. Any insights or recommendations would be greatly appreciated.

Capacitors MFG P/N:

1. CL32B106KBJNNWE - 10 uF - 50V rating.

2. C3216X5R1V226M160AC - 22uF - 35V rating.

Ferrite Bead MFG P/N:

1. BLM18KG260TN1D - 26ohm/6A

QUESTION UPDATE1: as shown in bobflux's answer, an electrolytic capacitor is mandatory to ensure stabilizing the voltage spike. I realized that ealier, but due to mechanical constraints, the maximal height I can place for such capacitor is 2.5 mm, and I couldn't find any electrolytic capacitor with such low height and also has high availablility in the market. I would love if someone can share a good example for such cap in case I missed it while searching.

QUESTION UPDATE2: following bobflux suggestion to use RT1720 Hot Swap Controller, I removed the previous circuit and made new one. here are few points:

1. I removed the SMCJ24CA because I thought there is no need for it anymore.

2. I expect that if the voltage crosses the 25.04V momentarily at the beginning (as a result of voltage spike), the VIN_ALW output will not be delivered, and that will not cause the DC-DC's go through over-voltage locking state.

3. I left the ferrite beads connected between GND and GNDC and also on the VIN_ALW_PHNX rail.

4. added 100nF (50V rated) capacitor at the input of RT1720, and 3x 22uF (35V rated) at the output.

My Questions:

7. Do I still need the input capacitors or previous amount of output capacitors?
8. Do I still need the TVS diode at the input?
9. Do I still need the ferrite beads?
10. Is there any redundant part that is not needed and I can remove (I have some space limitations).
11. Is there anything else I missed in the circuit?

Answer 1

still not sure how the TVS will help the VIN voltage not go above 28V, because the diode I chose has clamping voltage of 38.9V.

The diode's specs are:

Breakdown voltage at 1 Amp: min 26.70 max 29.50.

Max clamping voltage 38.9V at max peak current of 38.6A.

This does not sound good for your 28V max input DC-DC chip.

Now click https://ds.murata.co.jp/simsurfing/index.html?lcid=en-us

Go to "Ferrite beads", select your part number, download Spice netlist.

Here I plot two responses, one with the circuit as-is (I reduced the MLCC values to account for capacitance drop under bias) and one with a 100µF 0.2R ESR electrolytic cap. In the first case, as expected there is a large spike in the frequency response.

Without the electrolytic this translates into a large voltage spike which exceeds 28V by a large margin. The TVS dumps close to 30A. With the electrolytic, it's okay.

This simulation is not realistic for the following reasons:

• When the power connector is plugged, the current spike will saturate the ferrite beads, so they will not store as much energy as the simulator thinks. Thus the actual voltage spike will be lower.

• Cable inductance and power supply output impedance are not known exactly. I tried to put in reasonable values, but who knows.

• The electrolytic cap's ESR needed for good damping is quite critical, the response changes a lot with 0.1 or 0.3 ohms instead of 0.2 ohms, and this variation is very much within the margin of uncertainty on a capacitor ESR, or on the power supply's output impedance.

But the gist of it is, I'm not optimistic for the chances of survival of your 28V max input buck chip. It would be a lot safer to use a 36V max input one so the TVS can keep it safe. If you want to protect this 28V chip against the plug-in voltage spike, with a 24V supply, then you really don't have much margin.

Is it acceptable to place series resistors with only some of the capacitors? Are there any potential drawbacks to this approach?

It's okay, but normally you'd put the damping resistors on a cap that is much larger than the others, typically an electrolytic with appropriate ESR. If you put it on the smaller cap, the other ceramic caps (which have milliohm ESR) will dominate the response, and the resistor will do nothing.

Answer 2

Regarding damping, you have it backwards; it should be this way:

Damping goes on the largest not smallest capacitors. I believe I mentioned in a previous question, use C || (Cs + R) where Cs > 3C and R = sqrt(L/C). Here, Cs is 3 x 22uF and C is, at least 3 x 10uF, but the 30uF left of the FBs should likely be included in the total as well.

You may also be able to find aluminum polymer chips in low profile, and relatively high ESR; though they're mostly a low-voltage style I think, so maybe not. Worth a look.

The resistors can also be collected in common, though you might prefer individual ones, or parallel combinations, to keep stray inductance down, or maximize reuse of components (BOM item reduction).

I also highlighted the TVS connection: I don't understand why it's skew-connected across the FBs. Namely, L22-L23 are in the loop, but why not also L24-L25? Or neither (PHNX_DC_IN to GNDC)?

Regarding ESD, it is a high-impedance transient and these ferrite beads do nothing to it. Even large-value CMCs have little effect, as they rapidly saturate under the huge flux of a high-voltage discharge (or spark over themselves). 7.5 ohms (30 / 4 in parallel) certainly has no impact on a 8kV 330Ω ESD pulse here. The best value these FBs can provide, is a modest amount of DM filtering; if you need CM filtering, choose a CMC proper.

ESD is best solved by proper (RF/EMI) grounding of the PCBA and enclosure, and shielding, or protection and filtering, of all connectors. It's not something you can insulate your system from: it goes through the air itself (displacement currents; wave mechanics are very much a real thing with ESD), the only thing you can do is shunt it around the system.