# What is meant by Input clamp current/Output Clamp current in micro controller datasheet?

While reading a PIC data sheet, I found the parameters Input clamp current / Output Clamp current. Where do I consider these specifications?

• Can you provide a link to the data sheet and tell us which page this data is on please? Jun 3 '13 at 12:49
• pic 18f4550 datasheet page number 369 :ww1.microchip.com/downloads/en/DeviceDoc/39632e.pdf Jun 3 '13 at 12:50
• which page is this data? I searched the pdf and could find no reference to "Maximum Input clamp current" Jun 3 '13 at 12:52

It is an ESD circuit triggering limit specification.

Here is a snip from page 369 (labelled as 367):

Since these numbers are so low it's clearly not the current during the ESD event. Why would an ESD event be clamped at currents less than the maximum current rating of a driven output? Additionally once an ESD event is underway you're not going to be limiting it to just 20 mA!

Take into account that these are absolute maximum specs and the fact that these "clamp currents" are specified under the conditions that $V_I<0$ and $V_O>V_{DD}$ the logical conclusion is:

"Thou shall not take the pins below ground or above the upper rail IF you are capable of driving more that 20 ma. If you do so then the ESD circuits are going to trigger" - i.e it's the trigger conditions under which the on chip ESD circuits are going fire.

Some datasheets specify dv/dt rates as well.

Modern semiconductor pins have the challenge of protecting against ESD at lower voltages. The only real way of doing this is to have all the pins connected to an internal ESD rail via diodes (often in a half bridge configuration and sometimes a full bridge). You can't use a zener or clamping diode circuit as you can't control the breakdown voltage accurately enough for the lower voltages - below 3.3V. The solution is to have active circuitry that monitors the ESD rails and then clamps them together. This also allows an any-pin to any-pin clamping action.

These pins will be designed for currents that are well in excess of 100's of mA but they also have to be low capacitance to prevent undue loading of the drivers.

There is also an alternative explanation that these are the limits at which if exceeded will trigger latch up in the substrate. While possible in older processes this is not likely in modern processes. However, I don't know the process details so for completeness, this should be mentioned.

Most modern CMOS chips have reverse diodes to ground and power on each pin. This is to provide a path for static discharge without hurting the the more sensitive components on the IC, hopefully, most of the time, probably, if you're lucky.

There are probably two separate specs for these clamp diode currents. The absolute maximum section will tell you what the device can tolerate without getting damaged. This is the current the diodes can shunt around the rest of the chip without harm. The other spec will be in the operating section. This current will be much less because current thru these diodes can cause various problems to the operation of the device. Basically, in a practical sense you don't want these diode to conduct during operation.

• +1 for the hopefully, most of the time, probably, if you're lucky Jun 3 '13 at 14:02
• Most of your 2nd paragraph directly contradicts the datasheet. Your last sentence is fine. The pads cells in modern processes must be demonstrated to handle multiple Amps to be able to handle MM (Machine model) ESD. Care to edit? Jun 3 '13 at 17:10
• @rawbrawb: I'm not clear what you are saying. How does the datasheet disgree with what I said? I just checked, and abs max is 20 mA. I know I've seen a voltage and current diode clamp spec for other PIC, but this one just specifies the valid input voltage ranges limited to Vss and Vdd. That in effect says 0 forward bias on the diodes is allowed during operation. I still don't see how that contradicts what I said. Jun 3 '13 at 17:27
• as an aside, the DV's aren't mine. I think I've answered most of that in my own post. but .. the specs aren't different, The data is FROM the abs max section. We know it can't be a max current because these values are less than the drive currents. And then logic/experience kicks in as we know that ESD generates huge currents. I think what caught you out is the use of "clamping" that is obviously wrong. A 2KV ESD pulse "clamped" at 20 ma isn't doing anything for EOS. Jun 3 '13 at 19:37

Many chips have clamp diodes between I/O pins and the power rails. Such diodes can be a cheap way of providing a significant measure of ESD protection. Further, many chips connect the negative rail to a P-type substrate and the positive rail to N-type wells within it; each transistor's source and drain will form a PN junction with the substrate or well within which it resides, and PN junctions behave like diodes when the potential of the P side exceeds that of the N side by more than about 0.7 volts.

In some cases, the clamp diodes are constructed in such a way that current which flows through them will not affect any other operations of the chip. In other cases, current which flows forward through the PN junctions that serve as clamp diodes can cause unwanted currents to flow across other, reverse-biased PN junctions, in much the way that base-emitter currents in a PNP or NPN transistor will cause current to flow across the reverse-biased collector-base junction.

Unless the manufacturer specifies that a device will operate normally in the presence of clamp-diode currents, one should avoid having any non-trivial amount of current flow during any normal operating condition. On the other hand, if a device manufacturer believes a part will often be used in cases where it will be necessary to clamp relatively small amounts of currents (e.g. 10mA) to the rails, allocating the extra space to place the PN junctions in such fashion as to prevent such currents from causing unwanted current flows elsewhere may be worthwhile even if only 0.1% of the parts are used in places that would otherwise need a protection diodes.