2
\$\begingroup\$

I have the Xilinx Spartan-3AN Starter Kit and I need to use the on board DDR2 SDRAM (MT47H32M16CC-XX). Until now I only used Static RAM and this type of memory is new for me. Can someone explain me how this memory works? What are the differences compared with a SRAM?

\$\endgroup\$
6
  • \$\begingroup\$ Your question could probably use some generification. If you're simply asking "What do I have to do different for DRAM vs SRAM", or "What do I need to consider when designing a circuit using DRAM with a FPGA", I think it would be a lot more likely to get good answers. \$\endgroup\$ – Connor Wolf Jun 3 '13 at 14:01
  • \$\begingroup\$ You're right. I have edited the question. \$\endgroup\$ – Oceanic815 Jun 3 '13 at 14:11
  • \$\begingroup\$ @ConnorWolf: Actually, that isn't good advice. Generic questions such as you suggest would require long tutorial-style answers that aren't a good fit for the SE format. Here, we focus on answers to specific design problems. \$\endgroup\$ – Dave Tweed Jun 3 '13 at 14:12
  • \$\begingroup\$ @DaveTweed - Hmmm, good point. I still think "What do I need to do differently to use this DRAM then the SRAM I have used in the past" is a more generally useful question. Specifying one particular FPGA and DRAM parts number, when asking a question that seems to be about general practices seems a bit too localized to me, though. \$\endgroup\$ – Connor Wolf Jun 3 '13 at 14:15
  • \$\begingroup\$ @Oceanic815: The memory chip datasheet, Spartan chip datasheets, the Xilinx design tools and the example code all provide a lot of information about this topic. You need to read through this material and then ask here about specific issues that you're stuck on. Also, you need to provide some information about your application in order to get specific guidance. Do you just need the higher capacity of the SDRAM, or do you (also) need to wring the maximum possible bandwidth out of it? \$\endgroup\$ – Dave Tweed Jun 3 '13 at 14:19
1
\$\begingroup\$

Given the lack of detail in your question, here is a brief generic overview.

SDRAM, like SRAM, is a memory. To write to it, you present an address and some data, and to read from it, you present and address and get some data back some time later.

However, unlike SRAM, SDRAM requires both initialization/configuration at startup as well as ongoing refresh activity in order to operate correctly. Also, the internal structure imposes a multi-level addressing scheme involving banks, rows and columns. All of this means that you need to have a controller for the SDRAM inside your FPGA that manages all of these activities while working within the timing and sequencing rules imposed by the SDRAM chip. This controller generally takes the form of a fairly complex state machine that runs at the same speed as the SDRAM interface.

Xilinx provides a SDRAM controller generator as part of its design toolchain, and in some FPGAs, there is a dedicated, or "hard core" memory controller.

\$\endgroup\$
5
  • \$\begingroup\$ Thanks for your overview. Is it possible read a single data with the Xilinx soft core controllers or I have to read the entire memory bank? \$\endgroup\$ – Oceanic815 Jun 3 '13 at 14:41
  • \$\begingroup\$ You can read as little as one word of data at a time from SDRAM, but "random" accesses are a lot less efficient (in terms of bandwidth) than "burst" accesses, in which you read 2, 4 or 8 sequential words at a time. \$\endgroup\$ – Dave Tweed Jun 3 '13 at 14:45
  • \$\begingroup\$ So for my application (VGA controller) it's better to read many words at a time and store them in a little buffer on the FPGA, right? \$\endgroup\$ – Oceanic815 Jun 3 '13 at 14:48
  • \$\begingroup\$ Yes, that's the general technique used for frame buffers. The FIFO in the FPGA allows you to output pixels to the VGA interface on a strict schedule, even if the timing of the data coming from the SDRAM varies somewhat because of refresh and writing activities. \$\endgroup\$ – Dave Tweed Jun 3 '13 at 14:57
  • \$\begingroup\$ Thank you for the help, now I have a basic idea of what I have to do. \$\endgroup\$ – Oceanic815 Jun 3 '13 at 15:05
0
\$\begingroup\$

Practically, the main difference is that a SRAM controller is something you could write yourself in HDL. A DDR2 controller is orders of magnitude more complex, and so no one writes one themselves.

After you learn more about DDR2, You'll need to learn about Xilinx's Memory Interface Generator (MIG). This is a tool that is part of Core Generator, which is included with the free Xilinx ISE WebPack (all versions).

Here is a document that covers MIG for Spartan-3s (and several other older FPGAs). http://www.xilinx.com/support/documentation/ip_documentation/ug086.pdf

Definitely start looking that over. Then open 'Core Generator' and create a new project with your exact part number, package and speed grade. Then locate the MIG in the list of IP cores and double click it - this starts the MIG wizard. The wizard will give you an idea of all of the constraints and considerations involved in setting up the controller.

If you are using a development kit, all of this information should be available. If you are designing a new board with DDR memory, good luck!

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.