# Why are common mode chokes used in Ethernet magnetics

I’m trying to understand the reason the common mode choke is required in Ethernet magnetics. To understand, if we look at the schematic, with the common mode choke (horizontal coils) removed, we are left with the isolation transformer (vertical transformer) alone.

Now, if common mode signals are defined as currents flowing in the same direction on a wire pair, this would imply that signal currents flowing towards the PHY would come to the isolation transformer and cancel out. This means no common mode signals could cross the transformer and reach the PHY.

Similarly, looking in the opposite direction, (from PHY to towards the cable) common mode signals cannot exit onto the cable because the isolation transformer won’t transmit these through. So from that argument there is no need for common mode chokes!

There are however 2 ways I can think of where common mode signals could escape onto the cable.

1. If the lines are not perfectly balanced.
2. Stray fields from whatever circuit the magnetics is on coupling directly onto the cable side of the isolation transformer.

Assuming this is correct, the common mode choke would serve to reduce radiated emissions due to these effects?

I know that the Bob Smith terminations also serve a similar purpose, so if I am correct concerning the common mode chokes, why then would both be needed?

• There's a parasitic capacitance between the two windings on the transformer, for one thing. Commented Jun 7 at 2:13

The transformers are transmission line construction. That is, each winding is a twisted pair (or even quad), with the ends brought out and wired as shown.

For short time scales, we can consider the transmission line equivalent circuit. I won't draw this here (in part because CircuitLab doesn't have a TL primitive, alas), but suffice it to say: if we have a common-mode transient, we have both ends of one winding going "up" (say) at the same instant, and that change is transmitted immediately to the primary side in the same direction: the transformer has very little isolation at high frequencies, indeed the instantaneous CM impedance is Zo/2.

If the PHY side has good CMRR, this doesn't matter, though it does again matter if it doesn't have unlimited CMR (i.e., voltage range) -- which is a big concern for transients like ESD, where the rising edge is very fast indeed (~ns) and more than enough to blow out any small / unprotected semiconductor junction (~10kV, 10s A peak).

But neither [CMR or RR] is the case in general, so we want to improve CMRR of the transformer.

We connect another TL, this time in series so to speak, and wrap that around a core. This has no effect on the media: it's already a twisted pair, so the differential mode goes on its merry way without any change. But in the CM, now the isolation capacitance of the transformer, acts against the magnetizing impedance of the CMC, and we get significant filtering value.

The overall effect is, CMRR is dominated by isolation at low frequencies, and the CMC at high frequencies.

And I haven't yet mentioned balance. Inevitably, the transformer won't be twisted perfectly evenly, or the wires have different diameter (insulation or metal), or their lengths don't match, or the wire stubs tying to the package pins are a jumble, whatever -- in any case, there is likely some [CM-DM] mode conversion, and so CMRR is a term in noise rejection as well. The CMC again helps to improve this.

We could put a CMC on both sides of the transformer, to make it symmetrical; or just on the PHY side perhaps, but this has two drawbacks:

1. At least for traditional 10/100 style PHY, we need to draw CM current. Namely, the CT is VDDA referenced, and a push-pull connection is used to drive the line: a pair of MOSFETs pulling from either side towards GND. We could then use a three-line CMC (and indeed, these are used for PoE magnetics, though this is to avoid saturation due to DC bias).
2. Adding stub length at the PHY side is undesirable. There is a pretty generous margin to spare, here -- 10/100, and even 1000BASE-T, have quite low symbol rates, as "high speed" communications are concerned (down to ~8ns) -- so we can easily afford a fraction of a ns of stub length here or there. But it does add up, and we start with a minimum stub length in the transformer itself. Any PHY-side CMC, and trace length on the PCB, counts against us.

There is the special case where a full-bridge style driver is used -- mainly for GbE, but some 100BASE-T interfaces have adopted this architecture as well -- and here, usually the PHY side transformer is still center-tapped, but only a bypass cap is used, and the PHY drive is bipolar, symmetrical, so that a CMC could (presumably) be added here. This depends on the particular drive scheme, though, and it's better to avoid assumptions, and still minimize stub length in this case.

To better clarify that: consider what happens when one transistor turns on, and what's seen at the opposing transistor. At first, nothing happens; voltage drops at the same transistor, and that wave propagates along the PCB trace, from PHY pin to magnetics. In the transformer, that wave goes around once, reaches the CT, then propagates onward "upside down" (the two halves of the CT primary are two twisted-pair TLs wired in series end-to-end). The wave leaves the magnetics now positive-going, and finally propagates up to the opposing PHY pin, and is terminated by the 50Ω resistor there.

This round trip is the stub length: from any one pin driver to the output, there is a half-round-trip to get the wave into and across the transformer in the first place, and another half-round-trip to complete its travel up the stub. Hence, "stub".

A balanced drive can avoid this, by driving both lines simultaneously and complementary...ily. Which you can still analyze as two waves propagating around and back, but the environment and amplitudes are identical, so they cancel out; which is to say, we're not driving into the common mode. Checks out.