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I was going though these slides (page 3) which are adapted from Computer Architecture: A Quantitative Approach, 4th Edition by Patterson and Hennessey.

The topic is about Advanced Cache Optimizations. It suggests that we can get fast hit times via small and simple caches and the reason it gives is "smaller memory takes less time to index"

I could not understand why? I mean if tags are compared in parallel. Why should the size matter?

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  • \$\begingroup\$ Is it fine now? \$\endgroup\$ – a_fan Jun 4 '13 at 9:12
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    \$\begingroup\$ Which is quicker to count (index) 10 or 1000? \$\endgroup\$ – JIm Dearden Jun 4 '13 at 9:20
  • \$\begingroup\$ @JImDearden Thanks! I thought it works like base+(offset*word_size) or something like this. Why would 10 or 1000 matter in this formula? Perhaps that's where I am wrong \$\endgroup\$ – a_fan Jun 4 '13 at 10:16
  • \$\begingroup\$ The cache memory like any other memory needs to be addressed. The bigger the number of addresses you have to go (index) through the longer it takes. So a small very fast cache memory makes sense. My point was that counting to 10 is a lot faster than counting to 1000 - there is a limit to how fast you can count. \$\endgroup\$ – JIm Dearden Jun 4 '13 at 10:23
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    \$\begingroup\$ @JImDearden, I don't see were counting is involved when looking things in a cache (more precisely, all counting are moved in the space domain instead of the time one which would be used for a model). \$\endgroup\$ – AProgrammer Jun 4 '13 at 13:43
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At least two factors:

  • bigger caches means longer wires, so it takes more time for the information to travel (remember, at 1Ghz, light travel 30cm per cycle, and electrical signals are slower), both from the address to the memory cells, and from the memory cells to the place where the data is used.

  • if your cache is fully associative, that means that you have to address more comparators, increasing the load on the address lines and thus reducing the speed more than just what the wire length increase would hint.

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  • \$\begingroup\$ Even if there was no wire delay, address decoding time would slightly increase with each doubling of size (with unchanged associativity). \$\endgroup\$ – Paul A. Clayton Jun 4 '13 at 13:33
  • \$\begingroup\$ @PaulA.Clayton, why would you need decoding with a fully associative cache (with a partially associative one, you need to decode to know which of the lines are addressed of course), am I missing something there? (I know that I'm missing things at other places, the first being the eviction logic) \$\endgroup\$ – AProgrammer Jun 4 '13 at 13:41
  • \$\begingroup\$ Full associativity is rare in caches and becomes increasingly rare as size increases. (I did state "with unchanged associativity".) E.g., a 32 KiB cache with 64-byte blocks would require 512 ways to be fully associative--not exactly a practical design point. \$\endgroup\$ – Paul A. Clayton Jun 4 '13 at 13:49

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