# Slow clock edge causing issues with D flip flop behavior

I'm trying to use a D flip flop and a pushbutton as a simple switch. My goal is this: every time I press the button, the output of the FF will switch state.

I put a circuit together in a simulator and it worked fine. I implemented a debounce circuit for the switch that works nicely on its own, with my scope showing a fast and smooth rise with no bouncing.

Essentially, I have the switch pulled low and attached to the CLK input. When the button is pressed, the clock is pulled high, triggering the FF on the rising edge of this signal.

The ~Q output is connected straight to the D input. When the FF is triggered by the clock, ~Q takes on the opposite value of D. Therefore, the FF should switch values on each button press. Because the FF is only triggered by the rising edge of the CLK signal, I don't have to worry about D changing faster than I can release the button. All good in theory (and in my simulator).

So I bought a D FF and hooked it up to my breadboard, attached my button and passives, threw an LED on the output and ... it's wonky. It would either turn on or turn off upon a button press, with a somewhat equal probability.

I examined the CLK signal with my scope and believe I found the culprit. As the clock edge falls, it reaches a certain voltage and then goes through a ton of small oscillations. It seems that these oscillations keep registering as "rising edges" on the CLK signal, which would rapidly change the value of ~Q (and consequently, D). I interpret this as the reason why I can't predict the output of the current set-up - because I have no idea how many dozens of oscillations occur during the falling clock edge.

Examining the ~Q / D lines shows similar oscillating behavior upon the CLK going metastable.

I've tried attaching capacitors on the CLK, D, and ~Q lines in all sorts of combinations to try to smooth out the behavior. Nothing has worked. It seems the metastable state is ruining my circuit, which I've read a bit about and understand it to be a pretty serious issue in digital logic.

Are there any tried and true methods to eliminate this metastable behavior? Or any suggestions to pull my CLK signal down hard enough that it doesn't want to oscillate?

Any suggestions are appreciated. I'll keep plugging away.

• What technology of flip-flop are you using? TTL or CMOS? Jun 4, 2013 at 14:37
• Try 100 ohms in series with the switch and make sure you have power decoupling caps on the logic device. I've seen switches that short caps bounce logic circuits all over the place especially if you are powering the FF from close to the cap's positive end. My assumption is that it is not metastability but bad layout/placement of connections! Jun 4, 2013 at 14:45
• Dave, I linked to the datasheet above. It's CMOS. Jun 4, 2013 at 14:50
• Andy, thanks for the input, but any capacitor I add to the board only exacerbates the problem. Even placing the resistor between the switch and the clock pin doesn't help. Jun 4, 2013 at 19:06

You have unfortuantely run into a relatively subtle problem with this particular flip-flop. (BTW, this is not metastability; that's a different problem.) It's designed to operate at high speed over a wide range of supply voltages, and one of the compromises made in its design is that it has a rather strict requirement on the clock input transition speed.

If you look at section 9 of the datasheet, the input transition rate is given as 10 ns/V maximum. This means that you need to make the clock rise or fall by 5 volts in no more than 50 ns in order for the chip to operate correctly. With an RC time constant of 10 ms, you are about 6 orders of magnitude too slow.

• I think this is correct. I can get the CLK edge to rise up quickly enough, which explains why that's not giving me trouble. But the falling edge is really dictated by the amount of time it takes for the cap to discharge through the pull-down resistor, which is far longer than my allotted 50 ns. This is where the trouble begins. Interesting! Jun 4, 2013 at 16:07
• I think what's happening is that the master FF will pass the signal through whenever the logic level is much below VDD (rather than waiting for it to approach VSS), and the slave FF will pass through when the level is above VSS (rather than waiting for it to approach VDD). This allows it to capture and output the signal earlier than if it had to wait for full clock transitions, but means that the time the clock spends in the double-pass-through zone must be less than the time required for the signal to propagate through both latches. Jun 4, 2013 at 17:13
• The issue above only has one flip-flop. I'm not sure how your comment applies here. Jun 4, 2013 at 19:07
• Take another look at Figure 3 in the datasheet. Each of the two feedback loops represents a flip-flop or latch, and they're connected together by the TG in the middle. Individually, each one is triggered by a particular level of the clock signal. This arrangement is called master-slave, and is commonly used to create edge-triggered flip-flops. Jun 4, 2013 at 19:14

Is this truly metastability? I would rather call it a race condition within the FF master and slave cells at or near the FF switching point.

Using a RC for cleaning up the switch chatter is good, but it does slow down the $\dfrac{dV}{dt}$ of the clock which means that it transitions slowly through the switch point. You may or may not know this but you can use logic gates as high gain amplifiers if you bias them around the switch point. Any noise or ripple will cause down stream rapid signal swings. "cleaning up" the signal by filtering it more will only just exacerbate the situation.

Your solution? put a Schmidt trigger after the RC to drive the clock input.

Want to test out my hypothesis? put a inverter in place of the FF, connect your de-glitched switch and look at the output from the inverter.

• I vote for this answer because it has a useful solution: Add a Schmidt trigger gate. Also agree: This is not metastability. Jun 5, 2013 at 12:02
• @RolfOstergaard: The "problem" may not be metastability, but I wouldn't be surprised if the latch sometimes exhibits metastable behavior as well since the oscillating output fed back to the input would clearly not be meeting any sort of setup/hold requirements. Jun 5, 2013 at 16:54
• The actual term used in FF design literature is "race through". You could simply view it as an increased susceptibility to metastability because the dV/dt is so low that you've just opened up your window. It's a manifestation of signal propagation within the FF, regardless of what you want to call it. Jun 5, 2013 at 16:59