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The issue is that my RTC 32.768KHz Crystal is oscillating at ~31.5kHz to 33kHz, depending on Load Capacitor values from troubleshooting. This was verified using the RTC_output signal used for calibration. The RTC_output outputs at 512Hz, and my oscilloscope was measuring between 494Hz to 518Hz (depending on load capacitor).

  This puts my RTC at up to 3% inaccuracy, not 20 ppm accuracy as described by the datasheet.  

My question is if the large discrepancy is caused by the PCB layout or something else? For example, the GND plane does not fully isolate the circuit and traces on the back side.  

The crystal in use is Q13FC13500004 with a Cload value of 12.5pF. Using the formula for C1 and C2 values, I get the following: C1 = C2 = 2 * (Cload - Cstray), with Cstray being 5pF from the MCU datasheet, so I get 15pF. and I have varied C1 and C2 from 15pF to 20pF.  

I have also swapped out the crystal being used for one which uses the same Cload value.  

MCU used is an STM32G030C8T6  

Below is an image of the PCB layout and a screenshot of the RTC_output measurement

For my next revision, both the oscillator circuit AND the traces will be isolated by a GND plane.

PCB Layout

Oscilloscope Screenshot

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    \$\begingroup\$ The crystal you have picked is very, very low in power. How have you ensured that the power into the crystal does not exceed the limits specified in the data sheet. \$\endgroup\$
    – Andy aka
    Commented Jun 14 at 20:48
  • \$\begingroup\$ Definitely looks like a layout issue. It looks like there is a very tortuous pat for your load resistor grounds to get to you processor. These leads should be short. I would try putting short jumpers between the two pads labeled GND1 and the processor ground pin as a test. Also, you should not run signals under the crystal, but I doubt this is your problem since it is related to load capacitance. \$\endgroup\$
    – John Birckhead
    Commented Jun 14 at 20:56
  • \$\begingroup\$ I just checked the datasheet on pg 53 (in the link on the post) and it describes the different drive level settings. The configuration in my software defaults to "Low Drive Capability". However, I am unfamiliar with drive level for oscillators, so I need to read up on that. The datsheet specifies 250nA and 0.5 uA/V for gm for Low Drive Level and my oscillator specifies 0.1 uW as you note. Could there be an issue here? \$\endgroup\$
    – Kevin Lupercalia
    Commented Jun 14 at 21:00
  • \$\begingroup\$ @JohnBirckhead Yes, my next revision will look like this: PCB photo. So there won't be any signals running underneath and the paths should be minimized. And I don't have a load resistor on my circuit, though, is that something you'd recommend? \$\endgroup\$
    – Kevin Lupercalia
    Commented Jun 14 at 21:10

1 Answer 1

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I don't think you need a load resistor, but your grounds can still be improved. The three circled points in your layout should be together with short traces and not carrying current . The one on the right still has a tortuous path, and the pad on the left looks like its path is carrying the full processor current. Use a separate trace (a via if necessary) with a short, non-current carrying path back to your processor ground pin from each of your load resistors.

enter image description here

Good luck!

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  • \$\begingroup\$ Thanks so much for the detailed feedback. Does this new revision describe what you recommend? New Revision The tricky thing is on the chip, there is only a single ground out of all 48 pins. In the photo, I am showing how I have individual traces running back to the TOP of the GND pin. While I will route the rest of the processor GND from the bottom part of the pin. \$\endgroup\$
    – Kevin Lupercalia
    Commented Jun 14 at 22:04
  • \$\begingroup\$ That is much better! \$\endgroup\$
    – John Birckhead
    Commented Jun 15 at 1:29

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