Sigma-Delta ADC Sample/Conversion Rate to be clarified

Question

Basically a, let say 1MSPS, SAR ADC takes 1 million samples a second, and then we do some math with those samples (averaging, sorting/taking median, digital filtering, etc...) to obtain a good measurement result.

But with the Sigma-Delta ADC's, I am confused after reading from different manufacturer's notes.

In the link below, for example, it is said that:

Figure 3 shows a basic Σ-Δ ADC architecture, which continuously samples the analog input signal at the oversampling frequency (KfS) of the modulator, and its conversion output is the weighted average of a series of samples taken at KfS. Higher resolution Σ-Δ ADC has a longer conversion time since it requires 2N samples to complete a single conversion.

(https://www.analog.com/en/resources/technical-articles/precision-sar-sigma-delta-converters.html)

Does this mean a 20 bit Sigma-Delta ADC takes 2²⁰ samples to give me a single conversion result? And this result will be a weighted average of those 2²⁰ samples? That is I almost don't need to do any further math to obtain a cleaner result?

Sigma-Delta ADCs are generally said to be far more slower than SAR ADCs. I see there are many of them around 1 KSPS. Considering the explanation above, does this mean that a 1 KSPS Sigma-Delta ADC provides a single conversion result in 2²⁰ / 1000 seconds? Or, it provides a weighted average of 2²⁰ samples in 1/1000 seconds?

Could someone please explain it?

Answer 1

You're mixing up "sampling frequency of the ADC" and "oversampling frequency of the modulator". Those are different things.

A 1MSPS ADC will give you 1 million samples per second at the output of the ADC, where you read that into your microcontroller/FPGA/whatever. That's the "sampling frequency".

Internally, a Sigma-Delta ADC will use a higher frequency, the "oversampling frequency of the modulator". That's mostly an implementation detail, as someone using the ADC you don't usually have to care about that.

Somewhere in between those two is a different "oversampling" option, which some (not all) ADCs have. This is user-configurable, and if you turn it on it WILL reduce the sampling frequency you get. E.g. if you turn on x16 oversampling, then the ADC will take 16 samples at it's normal sampling frequency (say 1MSPS), and average those for you, and give you the samples at a lower rate (62.5kSPS in this example).