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I'm getting the following timing summary from the synthesis:

Timing Summary:
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Speed Grade: -1

   Minimum period: 9.982ns (Maximum Frequency: 100.180MHz)

   Minimum input arrival time before clock: 4.597ns

   Maximum output required time after clock: 4.364ns

   Maximum combinational path delay: 2.788ns

I want to improve that, is there a way to find the critical path and maybe buffer it up a bit?

I don't know what is the bottleneck..

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  • \$\begingroup\$ If you say what tool you are using (ISE or Vivado), I can help, you can generate the detailed timing report but it is different on the 2 tools. \$\endgroup\$ – FarhadA Jun 5 '13 at 14:45
  • \$\begingroup\$ the question title says ISE... \$\endgroup\$ – Brian Drummond Jun 5 '13 at 15:11
  • \$\begingroup\$ Sorry, I missed that :( \$\endgroup\$ – FarhadA Jun 5 '13 at 16:52
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You have to run the generate_timing report on your design to get the detailed report for your design. In ISE you do it by choosing Tools->Timing-Analyzer->PostMap

ISE Timing Analyzer

It will generate a report with the information you asked for.

For more accurate timing analysis of your design, you should look into the timing AFTER the P&R is done.

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The bottleneck will be shown in explicit and gory detail just a little further down the synthesis report, in the "critical path" section for each timing constraint.

But before you pay too much attention to that : the "minimum period" is suspiciously close to 100 MHz. I would check to see if you had specified a 100 MHz clock timing constraint, increase it to 120 or 150MHz or ... and re-synthesize first. If synth can meet your actual goal without help, that's a much more time-efficient way to work.

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