# Synthesis timing summary in Xilinx tool (ISE)

I'm getting the following timing summary from the synthesis:

Timing Summary:
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Minimum period: 9.982ns (Maximum Frequency: 100.180MHz)

Minimum input arrival time before clock: 4.597ns

Maximum output required time after clock: 4.364ns

Maximum combinational path delay: 2.788ns


I want to improve that, is there a way to find the critical path and maybe buffer it up a bit?

I don't know what is the bottleneck..

• If you say what tool you are using (ISE or Vivado), I can help, you can generate the detailed timing report but it is different on the 2 tools. – FarhadA Jun 5 '13 at 14:45
• the question title says ISE... – Brian Drummond Jun 5 '13 at 15:11
• Sorry, I missed that :( – FarhadA Jun 5 '13 at 16:52