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I'm working on a two-stage opamp constituted by MOSFET transistors. The important specifications for this project are

  • Open loop bandwidth of \$30 \: \text{MHz}\$
  • Closed loop gain of \$2\$
  • A standard deviation of less than \$1 \: \text{mV}\$ in the offset voltage when performing Monte Carlo simulation.

I have already calculated some values for the width and length of each transistor, and the bandwidth and gain specifications are fulfilled, but the offset voltage requirement is not met.

schematic

simulate this circuit – Schematic created using CircuitLab

I have tried making the length of the current mirror load transistors M7 and M8 large such that the resistance of those transistors become larger but it's still not enough.

What else can I do to decrease the offset voltage of my design?

Edit

I am allowed to give the transistors fingers and multipliers but am not allowed to add additional transistors to the design.

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  • \$\begingroup\$ How are you characterizing the offset? Maybe draw an schematic \$\endgroup\$
    – Designalog
    Commented Jun 16 at 9:39

1 Answer 1

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Assuming the offset voltage is originating from mismatch of the transistors and not from some systemic imbalance, you can parallel multiple transistors.

Ideally that would reduce the imbalance by the square root of the number of transistors. In practice, layout would be important, I should think.

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