# Calculating junction-to-ambient temperature rise for switching MOSFET

So I'm looking at datasheet's since I'm looking for a N-Channel MOSFET for a DC-DC Buck Converter that will be switching at 1.2MHz. Since the MOSFET will be used as a switch for the Buck Converter, I need to pay attention to the power loss on the FET from Conduction and Switching (both of which I can figure out separately). The Buck converter will be supplying 10A of current on the output, with the output voltage being 4.2V.

What I'm not understanding is the Max Junction-to-Ambient spec on some of the MOSFET's I've been looking at. For the AON6262E, it has both a Steady-State rating and transient rating for the Junction-to-Ambient temperature. I know this sounds like a dumb question, but I will still ask for the sake of asking. Since this MOSFET will be used as a switch that will turn on and off with a duty cycle between 20% and 50%, will I need to take the transient Junction-to-Ambient rating to account when calculating the temperature rise of the MOSFET?

Temperature rise is what happens after heat has conducted through the materials the MOSFET (die and package) is constructed from, what it's mounted on, and any heat sinking or convection flow along with it.

This takes time, so we need to specify over what time scale we're applying power, and where we're measuring the temperatures.

The RΘJA parameter is usually measured on a standard fixture, such as specified in JESD-51. (Industry standards are not usually publicly available, but surprisingly, Infineon seems to be hosting a part-7 at the moment: High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages | EIA/JEDEC ) They refer to 1 in2 2 oz. copper, which means more or less a "tab" or pour of copper attached to the tab/pad/drain pins of this area (i.e. about 2.5 cm square), 70 µm thick, on otherwise ordinary FR-4.

FR-4 has both poor thermal conductivity, and slow heat spreading (thermal diffusivity), so the amount and placement of copper plays a very important role in PCB thermal design.

For a PWM application, the extremely-short peaks due to switching, and the short duration pulses due to conduction, average out within the die itself (time constant of ~100s µs), so from the outside, you only need be concerned about general operating power level. This is quantified in the transient thermal impedance plot, Fig.15 in the datasheet. Basically, at 10 s, heat is still diffusing across the board, so some excess power is tolerable, but only for the corresponding short duration (seconds).

This is also over such a time scale that you could place a chip thermistor near the MOSFET, and monitor its temperature in-circuit, providing thermal protection. Again, there's quite some delay (~seconds) between the MOSFET itself and the thermistor reading, so you can't be too aggressive here, but you could indeed make use of the lower RΘJA figure in that case.

• Thank you for the detailed explanation. My biggest concern with finding a MOSFET was searching for one that had a low rise and fall time, since the switching power loss was a bigger factor for the thermal rise. It sounds like the Normalized Transient Thermal Resistance graph is what I want to reference whenever I'm dealing with PWM switching and thermal management for MOSFETs. Commented Jun 19 at 19:11
• Switching times are dominated by gate-loop resistance and inductance (and sometimes drain current); any time parameters provided can generally be ignored as it's rare one is operating at exactly the same conditions as they are measured at. They can however be used as representative data, relative to those conditions (switching time will generally be proportional to gate-loop resistance). You may also not want to switch in the absolute minimum time, due to limitations of physical layout, EMI emissions, load conditions, etc. Engineering is a process of compromise in nearly all matters. Commented Jun 19 at 22:08

In your case, use the steady-state rating. The transient rating would be, for instance, if you were building in brief overcurrent capacity on a marginal thermal design. Please take notice of the notes.