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Could someone help me to make a clock that has outputs like this

enter image description here

there are 3 clock outputs

I have a reference schematic here, and this clock has 4 output and it made up of 2 flip flops, it uses IC SN74LS74 as shown in the picture, the IC is used to divide the frequency by 4 and then it is possible to use those states using logic gates to give the correct output enter image description here

So I need the output are just 3 clocks, could someone help me to find a true states for this problem.

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  • \$\begingroup\$ Do the three clock pulses need to be strictly non-overlapping? \$\endgroup\$ – Dave Tweed Jun 5 '13 at 17:59
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How about using a decade counter like (74HC)4017? You use a single clock signal for input and you connect the first unused output to \$\overline{\text{RESET}}\$

enter image description here

So in your case you would connect "Decoded output 4" to \$\overline{\text{RESET}}\$ and use "Decoded output 0, 1 and 2" as output. The clock input must be four times higher than the desired output.

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  • \$\begingroup\$ @DaveTweed OK, so he has to loop back ouput 4 to \$\overline{\text{RESET}}\$. \$\endgroup\$ – jippie Jun 5 '13 at 17:59
  • \$\begingroup\$ The problem to be solved has only 3 states, you should undo your edit. See the first waveform diagram. \$\endgroup\$ – placeholder Jun 5 '13 at 18:06
  • \$\begingroup\$ @rawbrawb Actually the clock diagram in the question is not entirely clear about what happens after third clock pulse. I think/hope OP catches the idea. \$\endgroup\$ – jippie Jun 5 '13 at 18:44
  • \$\begingroup\$ @jippie thank you for answering my qustion, i can understand your idea so far, but my question is can this IC divide the frequency by 3 before it provide outputs shown in first picture in my question ? \$\endgroup\$ – Yogi Yosnita Jun 6 '13 at 13:28
  • \$\begingroup\$ Look at the timing diagram. Your clock is all the way up and the respective outputs are numbered 0-9. To shorten the sequence you connect the first unused pin to reset. \$\endgroup\$ – jippie Jun 6 '13 at 18:01
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This looks like a home work question - so here are some hints:

This is three state system, so at the least you can use 2 FF's (for a maximum of 4 states) and throw logic to sequence through each of the three states and avoid the 4th state. Or you can use 3 FF's and simplify the logic (i.e. that sequence just looks like a shift register propagating a pulse).

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  • \$\begingroup\$ There are four distinct states in the OP's diagram. \$\endgroup\$ – Dave Tweed Jun 5 '13 at 17:48
  • \$\begingroup\$ @DaveTweed 3 separate NOC's is three states NOT 4 see first waveform diagram. The 2nd schematic diagram is an example that he was wondering if he could modify and that does have 4 states. \$\endgroup\$ – placeholder Jun 5 '13 at 17:56
  • \$\begingroup\$ The four states are 100, 010, 001 and 000, and then the sequence (presumably) repeats. \$\endgroup\$ – Dave Tweed Jun 5 '13 at 18:02
  • \$\begingroup\$ Fair enough, I'm assuming he just sketched it up quickly and dropped the repeat. It would be unusual but as posed ... \$\endgroup\$ – placeholder Jun 5 '13 at 18:10
  • \$\begingroup\$ @DaveTweed maybe he just wants a one shot on each LOL \$\endgroup\$ – Andy aka Jun 5 '13 at 18:25

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