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I was reading through the datasheet of a boost converter, TPS61023 from TI.

In the "Input Capacitor Selection section", they give the following advice:

Datasheet section

Notably, TI advises against using only a ceramic capacitor at the input, citing that it could induce ringing when a load step is applied at the output. The recommended solution is to place an electrolytic bulk capacitor between the ceramic capacitor and the input pin of the boost converter.

I am confused why this advice is given. The claim is that is reduces ringing caused by the inductance of the input power trace, but electrolytic capacitors usually have a worse ESL/ESR than ceramics. Nowadays, ceramics can have a comparable capacitance to the electrolytics as well. I know that ceramic capacitors can have a piezoelectric effect but I have not seen that cited as an issue for SMPS input capacitors.

So, what is the reason for this manufacturer advice?

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  • \$\begingroup\$ You misread, it says to place electrolytic capacitance between the power source and the ceramic (not between the ceramic and input pin, the ceramic should be as close as possible). In other words: plain bulk input capacitance at the location where power enters the board. Which should be common practice whenever a board is fed by long leads anyway. \$\endgroup\$ Commented Jun 21 at 19:00
  • \$\begingroup\$ Alternatively, you can use a soft start to mitigate ringing/current spikes induced by power inputs (plugging cables and so on). This will however cause other issues, such as certain ICs needing a particular voltage rise rate to reliably start and so on. \$\endgroup\$
    – Wesley Lee
    Commented Jun 21 at 19:18
  • \$\begingroup\$ See: electronics.stackexchange.com/questions/713381/… \$\endgroup\$ Commented Jun 21 at 19:53

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The ESR is exactly the reason why.

Assume you have pure capacitor with no ESR and you connect it to a voltage supply with a wire which is a pure inductance, you get an LC oscillation which never dampens.

And ceramic caps have very low ESR.

If you add a non-ideal electrolytic capacitor with some much higher ESR, it will dampen the LC oscillation by dissipating the energy in the ESR, and also brings down the frequency of oscillation as there is now more capacitance.

Same effect can be sometimes mitigated by putting a small series resistance in series with the ceramic cap, maybe in the order of 0.1 to 1 ohms depending on the application. Sometimes you see this on power inputs to PCB and also sometimes you see this on linear regulator outputs because they require higher ESR than ceramic caps have as they are intended to be used with tantalum or electrolytic caps that have higher ESR.

So this ringing will always happen when you plug or unplug supply cables so it's not only about this specific SMPS IC or even about linear regulators. The LC voltage spikes during unplugging or plugging in are high enough to do damage to chips.

Also for the same reason, there is a requirement that in USB Type-C cables, any plug at the end of a cable must contain a 10nF capacitor, because a small capacitance helps with noise and bypassing of smaller voltage and current transients, but it is not high enough capacitance to cause longer and higher inrush current transients that would cause excessive voltage transients and ringing.

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  • \$\begingroup\$ This makes sense. If I am deriving the power input elsewhere on the PCB then I assume this become less of an effect as the inductance of the traces is much smaller? \$\endgroup\$
    – Mu3
    Commented Jun 22 at 9:23
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schematic

simulate this circuit – Schematic created using CircuitLab

Consider these two circuits. The current sink is a timed step current of 100mA.

enter image description here

The problem with the barely damped ringing with little resistive load is that the actual load of a switchmode power supply looks like a negative resistance so, under some conditions, the ringing can grow rather than be damped out.

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  • \$\begingroup\$ Is the blue line on the graph V1? The inserted picture has cropped the axis label for the blue line. \$\endgroup\$ Commented Jun 22 at 6:27
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    \$\begingroup\$ Yes, blue is V1 \$\endgroup\$ Commented Jun 22 at 6:33
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They're just suggesting extra capacitance to compensate for the inductance of the long leads. They may have in mind 100-470uF, which is problematic for ceramics but easy with electrolytics and tantalum. Capacitor technology may have improved since the datasheet was written. Ceramics are quicker to respond than 'lytics, but for ring suppression, they don't have to be that fast, as long as you have the ceramic as well.

BTW, the larger capacitors should be placed farther from the chip; note the above paragraph says to place them "between ceramic input capacitor and the power source." The smaller/faster the cap is, the higher the frequencies it will absorb, due to self-resonance--which, in practice, includes the PCB traces.

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    \$\begingroup\$ Actually the amount of capacitance is not the key, the dampening effect of the higher ESR of tantalums and electrolytics is. If you used 100-470uF worth of ceramics, indeed it would take a lot of space with multiple capacitors, but also make the problem worse with extremely low ESR which does not dissipate the pulse or ringing energy. \$\endgroup\$
    – Justme
    Commented Jun 21 at 20:52

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