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I have a "JFET enhanced" op-amp circuit shown below: JFET Enhanced" op-amp circuit

"JFET Enhanced" op-amp circuit

Similar to the circuit used in the TI app note: App Note

The circuit looks stable in SPICE with the phase margin shown below: Open Loop gain of U1 and phase margin

Open Loop gain of U1 and phase margin

On my test PCB it is currently not stable and oscillating at ~12MHz (Measured at U1 Output (V_JFET)).

I suspect that the cause is due to the ADA4805 maximum Capacitive Load Drive of 15pF.

There is probably a fair amount of stray capacitance on the PCB from the routing and also the JFE2140 has a Input capacitance (Ciss) (at Vds=5V) of 13pF.

I have two questions:

  1. Is the most likely cause of the instability due to the capacitive loading of the op-amp. Apart from changing C4/C10 values; Is there anything else I could try to stabilize this circuit?
  2. I expect adding an output resistor between the U1/U3 output and C4/C10 would not improve the stability, as the resistor is within the feedback loop. Is there anywhere else that I could add a resistor to improve the capacitive loading?

Thanks for any advice given, Chris.

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  • \$\begingroup\$ Why do you call your 2nd graph "phase margin" when it's clearly the phase response. \$\endgroup\$
    – Andy aka
    Commented Jun 25 at 15:27
  • \$\begingroup\$ There is no power supply decoupling. It is critical for this type of circuit. Also, look at GND trace widths. \$\endgroup\$
    – AnalogKid
    Commented Jun 25 at 15:30
  • \$\begingroup\$ The "phase margin" graph is generated in SPICE by measuring the phase shift and open loop gain after disconnecting the op amp output. (unless I made a mistake here) I can generate the closed loop phase response if needed; it will be different from the graph shown. \$\endgroup\$
    – Chris192
    Commented Jun 25 at 15:32
  • \$\begingroup\$ There is power supply decoupling on the PCB (although it's not drawn above). There is a 10u and 0.1u between the positive and negative rails and ground next to the op-amp. It's not drawn as the above is a screenshot from the SPICE simulation. \$\endgroup\$
    – Chris192
    Commented Jun 25 at 15:34
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    \$\begingroup\$ Phase margin is not a graph but, a point on the phase response graph when gain is unity. \$\endgroup\$
    – Andy aka
    Commented Jun 25 at 17:45

1 Answer 1

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You're using a 100MHz small-signal bandwidth, 160V/us op-amp. Layout is critical. We need to see it.

C4 should go directly between output and inverting input, skipping the jfet. Otherwise the slow jfet defeats the purpose of this stabilizing capacitor.

The circuit you're using was designed for an op-amp 20-50x slower than what you've actually installed.

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